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Kioxia Corporation

Industry researchasia · jp
Official website
Research library7linked papers
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Selected work

Representative Papers

Counterexamples to Local Reconstruction Gain as a Proxy for Final Fidelity in Residual Completion

Sep 28, 2026

This study investigates whether local reconstruction gain in residual completion serves as a reliable proxy for final model fidelity. Leveraging a frozen Qwen3 backbone, the authors conduct multi-level intervention experiments using both training-free RESA and learnable Top-K+φ methods. The work reveals a non-monotonic relationship between local optimization and global performance: improving local reconstruction accuracy at attention layers does not necessarily enhance output fidelity, and positive local gains can even coincide with degraded KL divergence. These findings challenge the validity assumptions underlying existing evaluation paradigms for sparse attention and clarify the inherent limitations of approximate completion in specific scenarios.

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Top-K Retrieval with Fixed-Size Linear-Attention Completion: Backbone- and KV-Format-Preserving Attention for KV-Cache Read Reduction

Apr 07, 2026

This work addresses the decoding bandwidth bottleneck in long-context generation caused by frequent reads of the key-value (KV) cache, which becomes especially severe when the cache is offloaded to GPU external memory. The authors propose a retrieval-completion attention mechanism that, without altering the model architecture or KV cache format, computes exact attention over the top-K tokens most relevant to the query along with fixed anchor tokens at the sequence boundaries. Contributions from intermediate regions are approximated using a fixed-size feature map constructed during the prefill phase, and a unified normalization recovers the full attention distribution. This approach effectively mitigates the softmax bias introduced by top-K retrieval while requiring no additional KV cache accesses. Under identical KV access budgets, it significantly outperforms pure top-K methods, with particularly notable gains in high-entropy attention heads.

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Revolutionizing Long-Term Memory in AI: New Horizons with High-Capacity and High-Speed Storage

Feb 18, 2026

Current AI systems commonly adopt a “extract-then-store” memory paradigm, which often discards task-irrelevant yet potentially useful information, thereby limiting the development of long-term memory capabilities. This work proposes a novel “store-then-extract-on-demand” paradigm that preserves all raw experiences in full, enabling flexible retrieval across multiple tasks. By incorporating mechanisms for aggregative analysis based on large-scale probabilistic experiences and cross-task experience sharing, the approach enhances memory utility without relying on new learning algorithms—instead, it reconfigures the memory system architecture itself. Preliminary experiments demonstrate significant improvements in adaptability, reuse efficiency, and knowledge discovery within the memory system, offering a promising pathway toward high-capacity, high-throughput long-term memory architectures for artificial intelligence.

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Analysis and Evaluation of Using Microsecond-Latency Memory for In-Memory Indices and Caches in SSD-Based Key-Value Stores

Oct 14, 2025

SSD-based key-value (KV) stores heavily rely on expensive host DRAM for indexing and caching, creating a cost bottleneck. This work investigates migrating these data structures to lower-cost secondary memory with microsecond-scale latency (1–5 μs), but faces the challenge of sustaining high KV throughput under such latency. Method: We propose a user-thread–based software prefetching mechanism that explicitly models and jointly optimizes prefetching and I/O scheduling—without requiring new hardware or protocol modifications—to effectively hide secondary memory latency. Contribution/Results: Using an FPGA-based tunable-latency memory platform, we validate our approach via microbenchmarks and a modified KV store. Results show near-DRAM throughput is maintained even at up to 5 μs memory latency. To our knowledge, this is the first work to demonstrate that microsecond-latency secondary memory can serve as a cost-effective, drop-in DRAM alternative—achieving this without custom hardware or modifications to the storage stack.

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Recent publications

Latest Papers

Counterexamples to Local Reconstruction Gain as a Proxy for Final Fidelity in Residual Completion

Sep 28, 2026

This study investigates whether local reconstruction gain in residual completion serves as a reliable proxy for final model fidelity. Leveraging a frozen Qwen3 backbone, the authors conduct multi-level intervention experiments using both training-free RESA and learnable Top-K+φ methods. The work reveals a non-monotonic relationship between local optimization and global performance: improving local reconstruction accuracy at attention layers does not necessarily enhance output fidelity, and positive local gains can even coincide with degraded KL divergence. These findings challenge the validity assumptions underlying existing evaluation paradigms for sparse attention and clarify the inherent limitations of approximate completion in specific scenarios.

0 citationsRead paper

Top-K Retrieval with Fixed-Size Linear-Attention Completion: Backbone- and KV-Format-Preserving Attention for KV-Cache Read Reduction

Apr 07, 2026

This work addresses the decoding bandwidth bottleneck in long-context generation caused by frequent reads of the key-value (KV) cache, which becomes especially severe when the cache is offloaded to GPU external memory. The authors propose a retrieval-completion attention mechanism that, without altering the model architecture or KV cache format, computes exact attention over the top-K tokens most relevant to the query along with fixed anchor tokens at the sequence boundaries. Contributions from intermediate regions are approximated using a fixed-size feature map constructed during the prefill phase, and a unified normalization recovers the full attention distribution. This approach effectively mitigates the softmax bias introduced by top-K retrieval while requiring no additional KV cache accesses. Under identical KV access budgets, it significantly outperforms pure top-K methods, with particularly notable gains in high-entropy attention heads.

0 citationsRead paper

Revolutionizing Long-Term Memory in AI: New Horizons with High-Capacity and High-Speed Storage

Feb 18, 2026

Current AI systems commonly adopt a “extract-then-store” memory paradigm, which often discards task-irrelevant yet potentially useful information, thereby limiting the development of long-term memory capabilities. This work proposes a novel “store-then-extract-on-demand” paradigm that preserves all raw experiences in full, enabling flexible retrieval across multiple tasks. By incorporating mechanisms for aggregative analysis based on large-scale probabilistic experiences and cross-task experience sharing, the approach enhances memory utility without relying on new learning algorithms—instead, it reconfigures the memory system architecture itself. Preliminary experiments demonstrate significant improvements in adaptability, reuse efficiency, and knowledge discovery within the memory system, offering a promising pathway toward high-capacity, high-throughput long-term memory architectures for artificial intelligence.

0 citationsRead paper

Analysis and Evaluation of Using Microsecond-Latency Memory for In-Memory Indices and Caches in SSD-Based Key-Value Stores

Oct 14, 2025

SSD-based key-value (KV) stores heavily rely on expensive host DRAM for indexing and caching, creating a cost bottleneck. This work investigates migrating these data structures to lower-cost secondary memory with microsecond-scale latency (1–5 μs), but faces the challenge of sustaining high KV throughput under such latency. Method: We propose a user-thread–based software prefetching mechanism that explicitly models and jointly optimizes prefetching and I/O scheduling—without requiring new hardware or protocol modifications—to effectively hide secondary memory latency. Contribution/Results: Using an FPGA-based tunable-latency memory platform, we validate our approach via microbenchmarks and a modified KV store. Results show near-DRAM throughput is maintained even at up to 5 μs memory latency. To our knowledge, this is the first work to demonstrate that microsecond-latency secondary memory can serve as a cost-effective, drop-in DRAM alternative—achieving this without custom hardware or modifications to the storage stack.

0 citationsRead paper