Selected work

Representative Papers

Characterizing High Bandwidth Flash for LLM Serving

Sep 30, 2026

This study addresses the memory capacity and bandwidth bottlenecks in large language model (LLM) serving, along with the challenges of KV cache reuse under agentic workloads. To this end, it proposes an HBM-HBF host-side tiered storage architecture leveraging high-bandwidth flash (HBF). By designing a buffer-cache-aware scheduling strategy to coordinate data placement and incorporating real-trace simulation techniques, the system achieves holistic optimization across performance, energy consumption, and device endurance. Experimental results demonstrate that the proposed architecture reduces task completion time by 36.1%–87.0%, yields 55.8% energy savings, and significantly extends the HBF write lifetime from 4.77 to 14.82 years.

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Formal Verification of an Out-of-Order Multiprocessor against an In-Order Weak-Memory ISA

Jul 21, 2026

This work addresses transient, architecturally illegal intermediate states that can arise in out-of-order multicore processors under weak memory models. The authors propose a core specification that abstracts microarchitectural redundancy as instruction sequences and validates correctness in two steps: first, proving that the processor implementation refines this specification; second, reducing system-level out-of-order execution and inter-core interleavings to sequential ISA semantics. This approach yields the first unbounded formal verification of equivalence between an out-of-order multicore processor and a sequentially consistent weak-memory ISA, effectively isolating the impact of illegal intermediate states. The entire verification is mechanized in the Rocq theorem prover and innovatively leverages a large language model agent to automatically generate proofs covering all possible out-of-order executions and concurrent interleavings.

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High-Level Synthesis of Efficient Pipelines with Visibility Control

Jul 21, 2026

This work addresses the limitations of existing high-level synthesis (HLS) tools in balancing sequential semantics with fine-grained control over pipeline design, which hinders optimization of power, performance, and area (PPA). The paper proposes a novel HLS approach based on visibility control that preserves a sequential programming model while enabling precise manipulation of pipeline structures and hazard-handling mechanisms through a unified visibility abstraction. This framework encompasses strategies such as stall insertion, bypassing, speculative execution, delayed commit, and register renaming. Experimental results on a RISC-V core, histogram computation, and an AES accelerator demonstrate that the generated pipelines significantly outperform those from state-of-the-art sequential-semantics-preserving HLS tools, achieving PPA metrics close to hand-optimized RTL implementations and enabling efficient design space exploration.

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AsyncOPD: How Stale Can On-Policy Distillation Be?

Jun 23, 2026

This work addresses the instability and performance degradation in asynchronous online policy distillation (OPD) caused by training on stale policy data. It is the first to demonstrate that the reverse KL divergence is highly sensitive to outdated data, whereas the forward KL divergence exhibits greater robustness. Building on this insight, the authors propose an efficient alternative that recomputes the KL signal using the current student model and introduces a multi-sample Monte Carlo estimator to balance bias and variance. The resulting open-source AsyncOPD framework achieves comparable accuracy to synchronous training while improving throughput by 1.6–3.8×.

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EfficientRollout: System-Aware Self-Speculative Decoding for RL Rollouts

Jun 17, 2026

This work addresses the high rollout latency in reinforcement learning caused by autoregressive sampling, which is exacerbated by evolving policies and dynamic batching that render conventional speculative decoding ineffective. To overcome these challenges, the paper proposes a system-aware self-speculative decoding framework that automatically constructs a draft model through quantization of the target model—eliminating the need for additional training. The framework dynamically enables or disables speculation based on real-time system states and adaptively adjusts the draft length according to the acceptance rate, thereby aligning with the dynamic nature of rollouts. Experimental results demonstrate that, without compromising final policy performance, the proposed method reduces rollout latency by up to 19.6% and end-to-end latency by 12.7% compared to an autoregressive baseline.

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Recent publications

Latest Papers

Characterizing High Bandwidth Flash for LLM Serving

Sep 30, 2026

This study addresses the memory capacity and bandwidth bottlenecks in large language model (LLM) serving, along with the challenges of KV cache reuse under agentic workloads. To this end, it proposes an HBM-HBF host-side tiered storage architecture leveraging high-bandwidth flash (HBF). By designing a buffer-cache-aware scheduling strategy to coordinate data placement and incorporating real-trace simulation techniques, the system achieves holistic optimization across performance, energy consumption, and device endurance. Experimental results demonstrate that the proposed architecture reduces task completion time by 36.1%–87.0%, yields 55.8% energy savings, and significantly extends the HBF write lifetime from 4.77 to 14.82 years.

0 citationsRead paper

Formal Verification of an Out-of-Order Multiprocessor against an In-Order Weak-Memory ISA

Jul 21, 2026

This work addresses transient, architecturally illegal intermediate states that can arise in out-of-order multicore processors under weak memory models. The authors propose a core specification that abstracts microarchitectural redundancy as instruction sequences and validates correctness in two steps: first, proving that the processor implementation refines this specification; second, reducing system-level out-of-order execution and inter-core interleavings to sequential ISA semantics. This approach yields the first unbounded formal verification of equivalence between an out-of-order multicore processor and a sequentially consistent weak-memory ISA, effectively isolating the impact of illegal intermediate states. The entire verification is mechanized in the Rocq theorem prover and innovatively leverages a large language model agent to automatically generate proofs covering all possible out-of-order executions and concurrent interleavings.

0 citationsRead paper

High-Level Synthesis of Efficient Pipelines with Visibility Control

Jul 21, 2026

This work addresses the limitations of existing high-level synthesis (HLS) tools in balancing sequential semantics with fine-grained control over pipeline design, which hinders optimization of power, performance, and area (PPA). The paper proposes a novel HLS approach based on visibility control that preserves a sequential programming model while enabling precise manipulation of pipeline structures and hazard-handling mechanisms through a unified visibility abstraction. This framework encompasses strategies such as stall insertion, bypassing, speculative execution, delayed commit, and register renaming. Experimental results on a RISC-V core, histogram computation, and an AES accelerator demonstrate that the generated pipelines significantly outperform those from state-of-the-art sequential-semantics-preserving HLS tools, achieving PPA metrics close to hand-optimized RTL implementations and enabling efficient design space exploration.

0 citationsRead paper

AsyncOPD: How Stale Can On-Policy Distillation Be?

Jun 23, 2026

This work addresses the instability and performance degradation in asynchronous online policy distillation (OPD) caused by training on stale policy data. It is the first to demonstrate that the reverse KL divergence is highly sensitive to outdated data, whereas the forward KL divergence exhibits greater robustness. Building on this insight, the authors propose an efficient alternative that recomputes the KL signal using the current student model and introduces a multi-sample Monte Carlo estimator to balance bias and variance. The resulting open-source AsyncOPD framework achieves comparable accuracy to synchronous training while improving throughput by 1.6–3.8×.

0 citationsRead paper

EfficientRollout: System-Aware Self-Speculative Decoding for RL Rollouts

Jun 17, 2026

This work addresses the high rollout latency in reinforcement learning caused by autoregressive sampling, which is exacerbated by evolving policies and dynamic batching that render conventional speculative decoding ineffective. To overcome these challenges, the paper proposes a system-aware self-speculative decoding framework that automatically constructs a draft model through quantization of the target model—eliminating the need for additional training. The framework dynamically enables or disables speculation based on real-time system states and adaptively adjusts the draft length according to the acceptance rate, thereby aligning with the dynamic nature of rollouts. Experimental results demonstrate that, without compromising final policy performance, the proposed method reduces rollout latency by up to 19.6% and end-to-end latency by 12.7% compared to an autoregressive baseline.

0 citationsRead paper