Institution profile

Slovak University of Technology

Academic institutioneurope · sk
Official website
Research library20linked papers
Opportunities0open roles
Selected work

Representative Papers

Deep Dictionary-Free Method for Identifying Linear Model of Nonlinear System with Input Delay

Jun 03, 2025International Conference on Process Control

Modeling nonlinear systems with input delays remains challenging due to the failure of conventional linear methods and the difficulty of constructing appropriate basis function dictionaries. To address this, we propose an LSTM-enhanced, dictionary-free deep Koopman framework. Our method eliminates reliance on predefined basis dictionaries by leveraging LSTM networks to automatically learn latent temporal dependencies between past inputs and states, thereby enabling linear approximation of nonlinear dynamics in a learned embedding space. Crucially, input delays are implicitly encoded within the Koopman operator learning process, obviating explicit delay feature engineering. Experimental results demonstrate that our approach achieves significantly higher prediction accuracy than extended dynamic mode decomposition (eDMD) on unknown nonlinear systems, while matching eDMD’s performance on systems with known dynamics—indicating strong generalization capability and robustness.

1 citationsRead paper

Automotive Hardware Attacks: An Architect's Guide to TARA

Oct 07, 2026

This study addresses the ambiguities in physical access path rating and inconsistencies in hardware attack assessment within the ISO/SAE 21434 standard by proposing a hardware-aware extension to the Threat Analysis and Risk Assessment (TARA) framework. The proposed method introduces path dominance relationships and a three-tiered hardware relevance gating mechanism (H0–H2), integrating side-channel analysis, fault injection, and debug interface exploitation into a unified threat model while establishing evidence-based rating rules to standardize security justification processes. Validation against ten publicly documented attack cases on a reference gateway architecture demonstrates that most threats originate from the misuse of debugging or update mechanisms rather than solely targeting cryptographic computations, thereby confirming the effectiveness of the proposed framework.

0 citationsRead paper

Guess My Weight: Profiled Side-Channel Recovery of Floating-Point Neural-Network Weights

Oct 03, 2026

This study addresses the challenge of recovering IEEE-754 floating-point neural network weights from embedded devices via side-channel attacks, where the vast candidate space renders extraction intractable. We propose a template attack targeting floating-point multiplication, employing multivariate Gaussian templates with Hamming weight leakage modeling. A novel coarse-to-fine hierarchical search mechanism tailored for the structured 32-bit floating-point space is introduced to achieve bit-level precise recovery of full-precision weights. Experimental evaluations on an Arm Cortex-M4 platform using ChipWhisperer-Lite demonstrate that only 171 power traces are required to attain a 99% recovery success rate, while 263 traces yield 100% exact reconstruction. This work overcomes the longstanding difficulty of extracting high-precision floating-point parameters through side-channel analysis.

0 citationsRead paper
Recent publications

Latest Papers

Automotive Hardware Attacks: An Architect's Guide to TARA

Oct 07, 2026

This study addresses the ambiguities in physical access path rating and inconsistencies in hardware attack assessment within the ISO/SAE 21434 standard by proposing a hardware-aware extension to the Threat Analysis and Risk Assessment (TARA) framework. The proposed method introduces path dominance relationships and a three-tiered hardware relevance gating mechanism (H0–H2), integrating side-channel analysis, fault injection, and debug interface exploitation into a unified threat model while establishing evidence-based rating rules to standardize security justification processes. Validation against ten publicly documented attack cases on a reference gateway architecture demonstrates that most threats originate from the misuse of debugging or update mechanisms rather than solely targeting cryptographic computations, thereby confirming the effectiveness of the proposed framework.

0 citationsRead paper

Guess My Weight: Profiled Side-Channel Recovery of Floating-Point Neural-Network Weights

Oct 03, 2026

This study addresses the challenge of recovering IEEE-754 floating-point neural network weights from embedded devices via side-channel attacks, where the vast candidate space renders extraction intractable. We propose a template attack targeting floating-point multiplication, employing multivariate Gaussian templates with Hamming weight leakage modeling. A novel coarse-to-fine hierarchical search mechanism tailored for the structured 32-bit floating-point space is introduced to achieve bit-level precise recovery of full-precision weights. Experimental evaluations on an Arm Cortex-M4 platform using ChipWhisperer-Lite demonstrate that only 171 power traces are required to attain a 99% recovery success rate, while 263 traces yield 100% exact reconstruction. This work overcomes the longstanding difficulty of extracting high-precision floating-point parameters through side-channel analysis.

0 citationsRead paper

MAECO-Lite: Modular Ontology for Dynamic Malware Analysis

May 29, 2026

This study addresses the semantic ambiguity and reasoning challenges in existing dynamic malware analysis standards—such as MAEC and STIX—stemming from their conflation of persistent artifacts with runtime events. To resolve this, the work introduces the Unified Foundational Ontology (UFO) into the domain for the first time and proposes MAECO-Lite, a lightweight, modular ontology that clearly delineates core concepts including malware samples, processes, actions, system artifacts, and MITRE ATT&CK techniques. Crucially, MAECO-Lite enforces a strict ontological separation between persistent entities and runtime events. Empirical validation using description logic-based concept learning algorithms demonstrates that MAECO-Lite significantly enhances reasoning performance while preserving semantic rigor, thereby achieving an effective balance between computational tractability and ontological clarity.

0 citationsRead paper