Technical Lead Manager, Machine Learning, Memory Subsystem Design

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. As Technical Manager for TPU DRAM, you will develop and validate high performance memory subsystems for upcoming machine learning products. In this role, you will provide guidance to a team of design and verification engineers, collaborate with cross-functional peers on its system level aspects, and interact with the larger DRAM ecosystem, including DRAM manufacturers and third party IP providers.

Lead, mentor and manage a team of RTL Design and DV Engineers developing DRAM subsystems including HBM.\\nCollaborate closely with the cross-functional teams (e.g., Design for Test, Signal/Power Integrity, Packaging, Physical Design, Software, Silicon Validation, Silicon Engineering) to plan and execute throughout the development cycle.\\nInterface with third party IP providers of memory related IP including controllers, physical layers, and verification models during the selection and implementation phases of projects.\\nInterface with DRAM manufacturers during the design and validation of DRAM subsystems.\\nDrive improvements in design methodologies, processes, and quality control measures.