About the job
In this role, you’ll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You’ll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems.
Responsibilities
Lead the PCIe microarchitecture and RTL development, ensuring high-performance designs that strictly adhere to Power, Performance, and Area (PPA) targets, coding standards, and quality guidelines.
Manage the full RTL lifecycle, including documentation and coding, while ensuring the design is sign-off ready for Lint, CDC, and synthesis.
Partner with system architects to integrate the PCIe subsystem, ensuring it meets chip-level bandwidth, latency, and power consumption goals.
Coordinate with Verification and Physical Design teams to develop test plans, leverage PCIe VIP, and achieve successful timing closure.
Resolve complex protocol issues and lead post-silicon bring-up to ensure link integrity and subsystem performance.
Qualifications
Minimum
Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
5 years of experience in ASIC design, including one project focused on PCIe logic.
Experience debugging RTL using Verdi/VCS and automating tasks via Python or Perl.
Experience in SystemVerilog/Verilog for RTL development and microarchitecture definition.
Experience with PCIe protocol layers (e.g., Transaction, Data Link, and Physical) or LTSSM.
Experience with Clock Domain Crossing (CDC), timing closure, or synthesis flows.
Preferred
Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
8 years of ASIC design experience, including 3 years in PCIe (Gen4/5/6) controller or protocol logic.
Experience with advanced RTL design, including multi-clock domains, timing closure, datapath optimization, and hardware/firmware partitioning.
Experience with cross-functional leadership, driving efforts with software/system teams from RTL development through silicon bring-up.
Experience in PCIe architecture, including Link Training and Status State Machine (LTSSM), TLP/FLIT pipelines, flow control, ordering rules, and performance tuning.
Knowledge of ASIC flow, SerDes, and scripting.