About the job
In this role, you’ll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You’ll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems.
Responsibilities
Lead effort for timing constraint creation and validation, timing analysis and timing Engineering Change Order (ECO) creation, and final timing sign-off for complex ASICs.\nDrive both static timing analysis methodology development and support, as well as chip implementation and timing signoff execution.\nDevelop, support and execute implementation flows around industry-standard static timing and parasitic extraction tools.\nInterface with the broader team to triage and resolve reported technical issues, escalating complex tool-related problems to Electronic Design Automation (EDA) vendors and deliver timely and effective solutions.\nLead collaboration with RTL design and DFT team for high quality integrations and timing constraints.
Qualifications
Minimum
Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.\n10 years of experience in static timing analysis (STA), including 5 years of experience in a technical leadership capacity.\nExperience achieving full-chip timing convergence and authoring, reviewing, or validating timing constraints (e.g., Synopsys Design Constraints (SDC)).\nExperience using tool command language (Tcl) commands for timing analysis, timing closure, parasitic extraction, noise glitch, or crosstalk.\nExperience using electronic design automation (EDA) tools (e.g., PrimeTime, Tempus, Timevision, or STAR-RC).\nExperience analyzing cross-chip clock distribution networks.
Preferred
Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.\n12 years of experience in the domain of static timing analysis and 5 years of experience in leading STA activities for SOC.\nExperience leading physical design or STA flow/methodology to successful tape-outs and shipping silicon.\nExperience analyzing data trends, semiconductor device physics, SPICE simulation, and full-chip static timing topics.\nExceptional track record of on-time STA sign-off and delivery within physical design execution cycles.\nDrove full-chip timing convergence, timing constraint validation, and complex timing ECO implementation and sign-off.