About the job
We are seeking a Sr. Staff Engineer, Photonic Link Co-Design to join our LSAE team. This is one of the most technically demanding roles at Lightmatter: you will own the end-to-end simulation, co-design, and laboratory verification of photonic-electronic links in Passage™ — from photonic device modeling through to full transceiver channel characterization in silicon. You will build and maintain the high-fidelity simulation infrastructure that links optical device performance to system-level BER and link margin, drive co-design between photonic and analog circuit teams, and close the loop between simulation and lab measurement on every tape-out. This role sits at the center of how Lightmatter ensures Passage links meet performance at every process corner — and is the technical anchor for photonic-electronic integration quality.
Responsibilities
Develop, own, and continuously improve electro-optic link simulation models covering photonic device, propagation, and channel BER — from electron to photon to electron.
Build multi-physics models that combine optical propagation (VPI Photonics, Lumerical INTERCONNECT / FDTD, sax), analog circuit behavior (Cadence Virtuoso / Spectre, Verilog-A) into a coherent link analysis framework.
Execute comprehensive corner analysis, Monte Carlo variation sweeps, and process-voltage-temperature (PVT) studies to bound link margin; generate actionable specification tightening recommendations for device and circuit teams.
Work closely with analog circuit designers to co-optimize transmitter driver and receiver front-end for the photonic device interface; drive joint simulation across the optical-electrical boundary.
Contribute to photonic link budgets end-to-end: optical power, modulation efficiency, receiver sensitivity, noise floor, and SNR/OSNR margins.
Contribute to simulation-to-silicon closure methodology for Passage optical links; author test protocols, define measurement sequences, and iterate link models against measured data across process splits and device corners.
Identify and diagnose root causes of link performance gaps — distinguishing photonic, electrical, and integration origins — and drive corrective design actions.
Author and review photonic link architectural specifications, co-design interface requirements, and design-entry criteria for photonic and circuit teams.
Contribute to Passage product-level link planning: propose photonic and electronic co-design opportunities to improve link margin, power efficiency, or yield.
Qualifications
Minimum
PhD in Electrical Engineering, Applied Physics, Physics, or a closely related photonics/optics discipline and 5+ years of experience; or MS + 8 years of directly relevant industry experience at a photonic IC, transceiver, or optical interconnect company.
Deep expertise in photonic device physics and system-level optical link design: silicon photonic modulators, Ge photodetectors, passive WDM components, optical amplifiers, and coherent or intensity-modulated link topologies.
Hands-on proficiency with photonic simulation: VPI Photonics, Lumerical FDTD / INTERCONNECT, or equivalent optical propagation and circuit co-simulation tools.
Experience with analog and mixed-signal simulation: Cadence Virtuoso / Spectre, Verilog-A behavioral modeling, or Keysight ADS for electrical-optical co-simulation.
Demonstrated experience developing and executing optical link budgets, corner analyses, and simulation-to-measurement closure workflows.
Demonstrated high-speed lab skills: vector network analyzers (VNA) / S-parameter characterization, optical spectrum analyzers, high-bandwidth real-time oscilloscopes, BER test sets, optical modulation analyzers (OMA), and optical power meters.
Proficiency in Python for simulation scripting, measurement automation, and statistical post-processing.
Excellent written and verbal communication; able to drive architecture and specification discussions with device and circuit teams.
Familiarity with SERDES architecture: equalization topologies (FFE, DFE, CTLE), CDR, and mixed-signal PHY co-design for high-speed interfaces.
Preferred
Silicon photonics tape-out and post-silicon characterization experience; familiarity with PDK-level device models and extracted simulation vs. measurement correlation.
Exposure to co-packaged optics (CPO), near-package optics (NPO), or optical I/O chiplet integration challenges.
Signal processing knowledge: DSP for optical communications, forward error correction (FEC), or PAM-4 / NRZ / coherent modulation format trade-offs and simulation.
Experience with Monte Carlo and statistical design methodologies in the context of photonic-electronic system co-design.