About the job
SambaNova RTL Design Engineers design component units of the Reconfigurable Dataflow Unit (RDU) ASICs behind our AI acceleration systems. You'll own blocks within a larger subsystem, contributing sections of the microarchitecture specification, writing and debugging the RTL, and carrying your blocks through implementation, tape-out, and silicon bring-up. You'll work alongside principal engineers, architects, design verification, and physical design, and take on larger blocks as you build depth in our architecture.
Responsibilities
Own blocks within a larger subsystem of the RDU AI accelerator
Contribute sections of the microarchitecture specification
Write and debug RTL for high-speed, high-performance ASICs
Carry blocks through implementation, tape-out, and silicon bring-up
Make design decisions that trade off power, performance, and area
Qualifications
Minimum
B.S. in Electrical Engineering, Computer Engineering, or Computer Science
5+ years of experience in ASIC RTL design
Solid foundation in computer architecture and digital logic design
Strong SystemVerilog RTL design skills for high-speed, high-performance ASICs
Experience making design decisions that trade off power, performance, and area
Knowledge of industry-standard interconnects and protocols including AXI, PCIe, Ethernet, and HBM or DDR
Experience with digital logic synthesis tools and static timing analysis
Proficiency with industry-standard tools for linting, clock domain crossing, and logical equivalence checking
Experience implementing SystemVerilog Assertions to check design intent
Familiarity with tools and simulators for hardware performance analysis and tuning
Familiarity with Git for managing release cycles
Scripting skills in Python and Linux shell
Preferred
M.S. or Ph.D. in Electrical Engineering, Computer Engineering, or Computer Science
Exposure to a full ASIC development cycle through tape-out and production silicon
Interest in or knowledge of AI workload acceleration techniques
Experience with low-power design techniques such as clock gating and DVFS at advanced process nodes
Exposure to emulation or FPGA prototyping platforms for pre-silicon validation