Differentiable Routability-Driven Package Floorplanning with Pin Assignment

2026-07-16

AI Summary

This work addresses the challenges in advanced packaging posed by high-density redistribution layers, where congestion in fanout regions is difficult to model accurately and existing pin assignment methods struggle to mitigate net crossings. To tackle these issues, the paper introduces, for the first time, differentiable optimization into the co-design of package placement and pin assignment, proposing an end-to-end joint optimization framework. This framework integrates a differentiable wirelength model with a fanout-aware congestion estimator, a gradient back-propagation mechanism for discrete die orientations, and a crossing-aware pin assignment strategy, all accelerated by a GPU-enhanced multi-strategy DPSO algorithm. Evaluated across all benchmark cases, the approach achieves 100% routability, with successful instances demonstrating up to a 23% reduction in wirelength compared to state-of-the-art baselines.

Abstract

As advanced packaging technology evolves, increasing interconnect density in redistribution layers (RDLs) makes routability critical to package floorplanning. Meanwhile, power integrity requirements often reserve fan-in regions for the power delivery network (PDN), forcing signal nets through fan-out regions and complicating routability estimation. Existing uniform grid-based congestion models cannot accurately characterize fan-out congestion, while previous pin assignment methods struggle to evaluate net crossings. We propose a differentiable routability-driven floorplanning and pin assignment algorithm for advanced packaging with fan-out routing. First, a differentiable wirelength minimization method directly models discrete chip orientations and back-propagates wirelength gradients to chip locations and orientations. It reduces wirelength under fixed pin selection while avoiding the bias of continuous-angle modeling. Second, a crossing-aware pin assignment method incorporates net-crossing cost into a multi-strategy DPSO algorithm and uses GPU-parallel cost evaluation to reduce wirelength efficiently. Finally, a differentiable routability maximization method constructs a congestion model tailored to fan-out routing and establishes a back-propagation path from congestion information to chip locations, thereby guiding routability optimization. Experimental results show that our method achieves 100% routability on all benchmarks. For cases successfully routed by the baselines, it reduces wirelength by up to approximately 23% compared with a leading floorplanning method equipped with our pin assignment flow.

Problem

• routability
• package floorplanning
• pin assignment
• fan-out routing
• congestion modeling

Innovation

• differentiable floorplanning
• routability-driven optimization
• pin assignment
• fan-out routing
• net-crossing awareness