MIREDO: MIP-Driven Resource-Efficient Dataflow Optimization for Computing-in-Memory Accelerator

2025-10-30

AI Summary

Dataflow optimization for Compute-in-Memory (CIM) architectures faces a dual challenge: an exponentially large design space coupled with stringent hardware constraints. Method: This paper proposes a systematic co-optimization framework based on Mixed-Integer Programming (MIP). It integrates hierarchical hardware abstraction and cycle-accurate latency modeling to jointly optimize DNN workload mapping, dataflow scheduling, and CIM unit-level constraints—overcoming the local optima limitation of conventional heuristic approaches. Contribution/Results: Its key innovation lies in explicitly encoding non-differentiable architectural constraints as MIP formulations and enabling cross-layer trade-offs among resources, bandwidth, and latency. Evaluated across diverse mainstream DNN models and CIM hardware configurations, the framework achieves an average 2.7× speedup (up to 3.2×), significantly narrowing the gap between theoretical peak efficiency and realized system efficiency. It establishes a verifiable, scalable, and automated optimization paradigm for practical CIM accelerator deployment.

Technology Category

• Machine Learning: Hardware-aware ML
• Constraint Satisfaction and Optimization: Distributed CSP/Optimization
• Search and Optimization: Mixed Discrete/Continuous Search

Application Category

• Economics, Online Markets and Human Computation: Architectures and workflows that use LLMs for crowd work
• Graph Algorithms and Modeling for the Web: Efficient manipulation of static and dynamic Web-related graphs
• Systems and Infrastructure for Web, Mobile and WoT: Data management and stream processing for Web, mobile and wireless applications

Abstract

Computing-in-Memory (CIM) architectures have emerged as a promising solution for accelerating Deep Neural Networks (DNNs) by mitigating data movement bottlenecks. However, realizing the potential of CIM requires specialized dataflow optimizations, which are challenged by an expansive design space and strict architectural constraints. Existing optimization approaches often fail to fully exploit CIM accelerators, leading to noticeable gaps between theoretical and actual system-level efficiency. To address these limitations, we propose the MIREDO framework, which formulates dataflow optimization as a Mixed-Integer Programming (MIP) problem. MIREDO introduces a hierarchical hardware abstraction coupled with an analytical latency model designed to accurately reflect the complex data transfer behaviors within CIM systems. By jointly modeling workload characteristics, dataflow strategies, and CIM-specific constraints, MIREDO systematically navigates the vast design space to determine the optimal dataflow configurations. Evaluation results demonstrate that MIREDO significantly enhances performance, achieving up to $3.2 imes$ improvement across various DNN models and hardware setups.

Problem

• Optimizing dataflow for computing-in-memory DNN accelerators
• Addressing design space complexity and architectural constraints
• Bridging theoretical and actual system-level efficiency gaps

Innovation

• MIP formulation for dataflow optimization problem
• Hierarchical abstraction with analytical latency model
• Joint modeling of workloads and CIM constraints