Hardware.jl - An MLIR-based Julia HLS Flow (Work in Progress)

2025-03-12

AI Summary

Co-design of scientific algorithms and hardware accelerators faces challenges including high domain expertise requirements, substantial engineering effort, and prolonged iteration cycles. This paper introduces the first open-source, permissively licensed end-to-end high-level synthesis (HLS) toolchain for Julia, built atop MLIR and deeply integrated with Julia’s compiler infrastructure to automatically synthesize synthesizable Verilog from a subset of native Julia code. Methodologically, it combines custom domain-specific language (DSL) translation, multi-level intermediate representation (IR) optimizations, and integration with open-source EDA toolchains. Key contributions are: (1) fully automated HLS of Julia numerical kernels to hardware, eliminating manual RTL design; (2) compilation latency reduced by an order of magnitude compared to conventional HLS flows; and (3) significantly lowered barriers to FPGA/ASIC development for scientific computing, enabling—for the first time—the closed “algorithm-to-hardware” workflow.

Technology Category

• Machine Learning: Hardware-aware ML
• Natural Language Processing: Code Generation / Program Synthesis from Natural Language
• Humans and AI: Other Foundations of Human Computation & AI

Application Category

• Systems and Infrastructure for Web, Mobile and WoT: Experiences and lessons learnt from Web-based algorithms and system deployments
• Graph Algorithms and Modeling for the Web: Algorithms and analysis for heterogeneous, signed, attributed, multi-relational, temporal, higher-order, and annotated Web-related graphs
• Economics, Online Markets and Human Computation: Economic ramifications for generative AI infrastructure and applications

Abstract

Co-developing scientific algorithms and hardware accelerators requires domain-specific knowledge and large engineering resources. This leads to a slow development pace and high project complexity, which creates a barrier to entry that is too high for the majority of developers to overcome. We are developing a reusable end-to-end compiler toolchain for the Julia language entirely built on permissively-licensed open-source projects. This unifies accelerator and algorithm development by automatically synthesising Julia source code into high-performance Verilog.

Problem

• Co-developing algorithms and hardware accelerators is complex.
• High engineering resources slow down development pace.
• Unifying Julia code synthesis into Verilog for efficiency.

Innovation

• MLIR-based Julia HLS flow
• Reusable end-to-end compiler toolchain
• Automatic Julia to Verilog synthesis