SIMT/GPU Data Race Verification using ISCC and Intermediary Code Representations: A Case Study

2025-03-11

AI Summary

Existing static analysis tools for detecting data races in GPU parallel programs—arising from SIMT execution—rely on language-specific frontend adaptations, limiting their generality. Method: This paper proposes a memory-model-aware static verification approach based on LLVM IR, an intermediate representation that bypasses language frontends to enable cross-language, unified analysis. Contribution/Results: We present the first systematic evaluation of LLVM IR’s capability to support precise SIMT data race detection while preserving sufficient semantic and memory-model fidelity. Our method is validated across ISCC, CUDA C++, and Julia/CUDA.jl, demonstrating consistent detection of race patterns in the GeSpMM algorithm across all three languages. Results confirm that LLVM IR provides a robust foundation for high-precision, language-agnostic data race detection—effectively bridging high-level abstractions with low-level memory-model rigor.

Technology Category

• Machine Learning: Hardware-aware ML
• Computer Vision: Language and Vision
• Data Mining & Knowledge Management: Scalability, Parallel & Distributed Systems

Application Category

• User Modeling, Personalization and Recommendation: Large Language Models (LLM) for user modeling and recommendation
• Graph Algorithms and Modeling for the Web: Foundation models and LLMs for Web-related graphs
• Semantics and Knowledge: Data modeling to support human-machine intelligence, including LLMs agents, intelligent system behavior, explanations, and user-friendly interactions

Abstract

It is often difficult to write code that you can ensure will be executed in the right order when programing for parallel compute tasks. Due to the way that today's parallel compute hardware, primarily Graphical Processing Units (GPUs), allows you to write code. It is easy to write code that may result in one thread reading or modifying data before it should, thus resulting in a data race. It would be useful to have a tool that could verify that the code will execute as expected. However, most static analysis done at the language level has to be completely retooled to work on a different languages. Therefore, it would be of great use to be able to perform verification and analysis on the Memory Model of a parallel compute code, in a lower level intermediary representations that most languages pass through on their way to something that the GPU hardware can understand. This body of work aims to deal with the question of if there is still enough of the information in the intermediary representations to be able to perform memory model verification to check for data races. To determine this we plan to analyze as a case study the GeSpMM Sparse Matrix Multiplication Algorithm, implemented in CUDA C++ with the LLVM compiler and Julia with CUDA.jl.

Problem

• Verify SIMT/GPU code execution order to prevent data races.
• Analyze intermediary code representations for memory model verification.
• Case study on GeSpMM algorithm in CUDA C++ and Julia.

Innovation

• Uses ISCC for SIMT/GPU data race verification
• Analyzes intermediary code representations for memory model
• Case study on GeSpMM algorithm with CUDA C++