🤖 AI Summary
This study addresses the trade-off between computational overload and latency caused by immediate task acceptance in dynamic multi-robot task allocation. We propose a batch-based task acceptance merging mechanism integrated with the Consensus-Based Auction Algorithm (CBAA). Hardware-in-the-loop experiments conducted on AGX Orin and RP2040 platforms systematically quantify the nonlinear effects of merging strategies on latency and computational load under varying processing capacities. Results demonstrate that this mechanism significantly reduces processor load in high-demand scenarios but introduces additional latency when tasks arrive sparsely, revealing the platform-dependent efficacy of merging strategies. These findings provide empirical evidence for real-time task scheduling in resource-constrained systems.
📝 Abstract
Multi-robot task allocators in dynamic missions commonly admit newly released tasks immediately, potentially invoking allocation for each new arrival. We evaluate task-admission coalescing as a mechanism for controlling allocator processor work while accounting for target-service latency, using CBAA, ACBBA, PI, and HIPC as a representative MRTA suite. The study comprises a 3,000-mission AGX Orin campaign with measured computation delay, 3,000 paired zero-compute missions, and a 96-mission Pololu 3pi+ RP2040 allocator hardware-in-the-loop campaign. Immediate (Eager) admission is compared with thresholds of two, four, and eight tasks and a four-task policy with a 10-s waiting bound across three arrival rates. Across the AGX experiments, coalescing reduces both allocator calls and processor work in 31 of 48 evaluated conditions, although the magnitude of the saving varies by allocator. The principal cost appears under sparse arrivals, where four-task batching increases online-target mean latency by 20.08-23.57 s, predominantly through admission waiting. Bounded admission reduces mean work in ten of twelve allocator-load conditions, including a 19.35% reduction with a 1.40-s mean latency increase for high-arrival HIPC. RP2040 experiments show that this tradeoff can become more favorable as processor constraints tighten. Across four matched medium-arrival HIPC scenarios, Count b=4 reduces mean RP2040 work by 59.85% and service latency by 39.47%, while the corresponding AGX cases increase latency by 27.69%. These results show that the usefulness of task-admission coalescing depends on arrival intensity, allocator-specific behavior, and the relative cost of computation on the execution platform.