U-Sonic: An Open-Source 8-Channel Ultrasound Transmit IP in a 130 nm RISC-V SoC

2026-10-01

AI Summary

This study addresses the reliance of multi-channel synchronous excitation for miniaturized ultrasound probes on proprietary hardware or resource-constrained microcontrollers by proposing an open-source digital ultrasound transmit IP core integrated within a RISC-V SoC. The design employs a parameterized architecture supporting up to 16 channels, enabling programmable pulsing, composite bipolar and gated excitation schemes alongside precise synchronization control. Verified through Verilator simulation, FPGA prototyping, and synthesis in IHP 130nm technology, an eight-channel instance occupies only 14.3% of the SoC area while maintaining functional correctness. With the complete RTL stack and accompanying software released as open source, this work provides a highly flexible, low-cost open-hardware solution for miniaturized ultrasound systems.

Abstract

Miniaturized ultrasound (US) probes require programmable and synchronized transmit (TX) excitation across multiple elements, while existing compact platforms often rely on limited microcontroller (MCU) pulse generators or closed-source fixed-function pulser devices. We present U-Sonic, an open-source digital US TX peripheral integrated into a 32-bit RISC-V system-on-chip (SoC). The implemented SoC integrates 8 pulser cores, while the parameterized architecture supports up to 16 channels. Each core generates single- or dual-tone bursts with programmable period, duty cycle, pulse count, polarity, and idle level, together with optional inverted stop pulses for active damping. A shared memory-mapped Open Bus Interface (OBI) enables synchronous start and stop of arbitrary channel subsets and supports composite bipolar, gated, and three-level excitation schemes. Functional correctness was verified in Verilator against a Python golden model over 4379 checked cycles across directed and randomized configurations, and confirmed on a Terasic DE10-Lite field-programmable gate array (FPGA). The design was synthesized and placed-and-routed in IHP 130 nm. The post-layout area in kilo gate equivalents (kGE), scales as 1.65 kGE plus 1.66 kGE per channel. The 8-channel instance occupies 14.9 kGE, corresponding to approximately 14.3% of the 104 kGE SoC. The register-transfer level (RTL), register descriptions, verification collateral, and software support are released as open source.

Problem

• miniaturized ultrasound probes
• transmit excitation
• multi-channel synchronization
• programmable pulser
• RISC-V SoC

Innovation

• Ultrasound Transmit IP
• RISC-V SoC
• Open-Source Hardware
• Parameterized Architecture
• Active Damping