Open-Source Multi-Wire SPI Readout for Wearable Ultrasound Probes

2026-10-01

AI Summary

This study addresses the data transmission bandwidth bottleneck between FPGAs and wireless controllers in wearable ultrasound probes by proposing an open-source multi-line SPI readout interface. The method emulates serial flash memory protocols to ensure compatibility with microcontroller architectures, employing a configurable dual/quad-channel load-stage design combined with clock domain crossing and sample reassembly techniques to achieve high-bandwidth, low-power transmission. Validation on the Kria K26 platform demonstrates successful integrated operation at 5 MHz and error-free standalone transmission up to 66 MHz. All HDL code has been released as open source. This work provides an efficient data transmission solution for wearable ultrasound systems while establishing clear directions for future optimization.

Abstract

Wearable ultrasound probes must transfer increasingly large acquisition payloads while maintaining compact, low-power electronics. In TinyProbe, the current bottleneck in data transfer occurs between the acquisition FPGA and the wireless system controller. This work presents an open-source, multi-wire SPI readout interface that uses serial command and address phases followed by a build-time-selectable dual- or quad-lane payload phase that is intended to address this bottleneck by increasing the potential bandwidth over the wifi limit while retaining compatibility with the Microcontroller-centric wearable US architecture. The interface emulates a serial flash memory, enabling compatibility with a broad range of microcontroller families and their existing peripheral interfaces. On the FPGA, the data path connects the existing acquisition FIFOs to the SPI interface through clock-domain crossing, sample reshaping, and packing into 32-bit words. Dual-SPI readout is integrated into the existing IGLOO2/SiWG917 TinyProbe architecture and verified at an SCLK frequency of 5 MHz. A separate Kria K26 testbed is used to characterize the FPGA SPI interface independently of the acquisition and wireless subsystems, demonstrating error-free transfers at SCLK frequencies up to 66 MHz. These measurements identify the SiWG917 multi-lane SPI implementation as the next bandwidth-limiting component and motivate a future upgrade of the system controller. The HDL and MCU implementations are released under a permissive open-source license.

Problem

• wearable ultrasound
• data transfer bottleneck
• multi-wire SPI
• bandwidth limitation
• FPGA

Innovation

• Multi-wire SPI
• Wearable ultrasound
• FPGA readout interface
• Open-source HDL
• Bandwidth optimization