Timing-Driven Logic Remapping with Local Physical Context

2026-10-01

AI Summary

This study addresses the inadequacy of post-layout mapping decisions in accounting for surrounding timing constraints, fanout loads, and interconnect effects. To overcome this limitation, it proposes a local remapping framework that couples discrete search with physical feedback. The approach first isolates timing-critical regions and employs continuous relaxation to prune the search space. It then leverages mixed-integer programming to jointly optimize logic cuts, signal polarities, and library cell selection, modeling delays based on estimated placements. Finally, a closed-loop verification process encompassing legalization, routing parasitic estimation, and timing analysis is conducted to guide subsequent iterative searches. This work thereby achieves precise, physically aware, and timing-driven logic remapping.

Abstract

The timing behavior of a mapped circuit depends on both its logic implementation and the physical environment in which that implementation is realized. Revisiting mapping decisions after placement therefore requires a search procedure that accounts for surrounding timing constraints, fanout loads, and interconnect effects. We study local remapping in this setting and develop a framework that couples discrete mapping search with physical implementation feedback. Timing-critical regions are isolated through bounded windows whose interfaces retain the context of the surrounding circuit. Within each window, a mixed-integer formulation jointly selects logic cuts, signal polarities, and library cells under a delay model informed by estimated locations and interconnect parasitics. A continuous relaxation filters the search space before discrete optimization produces alternative implementations with similar modeled timing and different structural choices. These implementations are reconstructed and assessed through legalization, routing-based parasitic estimation, and timing analysis. Physically validated improvements are incorporated into the design, and the updated context guides subsequent searches. The framework provides a systematic way to revisit local logic implementations while accounting for their interaction with an existing placement.

Problem

• timing-driven remapping
• local physical context
• logic mapping
• interconnect parasitics
• post-placement optimization

Innovation

• Timing-Driven Remapping
• Mixed-Integer Formulation
• Local Physical Context
• Continuous Relaxation
• Interconnect Parasitics