Tiny Chiplets Enabled by Packaging Scaling: Opportunities in ESD Protection and Signal Integrity

2025-11-13

AI Summary

Conventional I/O circuits—integrating ESD protection and signal transmission—impose substantial area overhead in 2.5D/3D heterogeneous integration, severely hindering chiplet miniaturization below 100 mm². Method: Starting from chiplet interface reliability design, this work co-optimizes ESD protection and signal integrity. Leveraging package-level parasitic extraction and SPICE simulation, we quantitatively analyze electrostatic stress distribution and high-frequency signal degradation mechanisms, enabling the design of compact on-die ESD structures and low-overhead interconnect topologies. Contribution/Results: Experimental validation demonstrates >40% reduction in interface area while maintaining robust ESD resilience (e.g., HBM ≥ 2 kV) and signal integrity (e.g., <1 dB insertion loss up to 20 GHz). The approach supports high-density chiplet reuse, enhancing system integration density and energy efficiency without compromising reliability.

Technology Category

• Machine Learning: Hardware-aware ML
• Constraint Satisfaction and Optimization: Distributed CSP/Optimization
• Search and Optimization: Distributed Search

Application Category

• Systems and Infrastructure for Web, Mobile and WoT: Energy management for devices in mobile Web and WoT environments
• Security and Privacy: Large-scale security measurements
• Economics, Online Markets and Human Computation: Incentives in network design for Web infrastructures and ecosystems

Abstract

The scaling of advanced packaging technologies provides abundant interconnection resources for 2.5D/3D heterogeneous integration (HI), thereby enabling the construction of larger-scale VLSI systems with higher energy efficiency in data movement. However, conventional I/O circuitry, including electrostatic discharge (ESD) protection and signaling, introduces significant area overhead. Prior studies have identified this overhead as a major constraint in reducing chiplet size below 100 mm2. In this study, we revisit reliability requirements from the perspective of chiplet interface design. Through parasitic extraction and SPICE simulations, we demonstrate that ESD protection and inter-chiplet signaling can be substantially simplified in future 2.5D/3D packaging technologies. Such simplification, in turn, paves the road for further chiplet miniaturization and improves the composability and reusability of tiny chiplets.

Problem

• Conventional I/O circuitry causes significant area overhead in chiplets
• ESD protection and signaling complexity limits chiplet miniaturization below 100mm²
• Current reliability requirements constrain tiny chiplet composability and reusability

Innovation

• Simplified ESD protection using packaging scaling
• Reduced inter-chiplet signaling via parasitic extraction
• Miniaturized chiplets through simplified interface design