P4-TAS: P4-Based Time-Aware Shaper for Time-Sensitive Networking

2025-11-13

AI Summary

Commercial Time-Sensitive Networking (TSN) switches implement the Time-Aware Shaper (TAS) in hardware, yet critical internal latencies—particularly queue activation delays—remain opaque, severely limiting deterministic scheduling accuracy. To address this, we propose P4-TAS: the first high-precision TAS prototype implemented on programmable ASICs using the P4 language. Our approach introduces an in-switch control-frame generation mechanism to enable nanosecond-precision periodic queue scheduling and presents the first systematic, quantitative model of on-chip latency sources. Integrated with an MPLS/TSN translation layer, P4-TAS achieves line-rate forwarding at 400 Gb/s. Experimental evaluation demonstrates scheduling errors under 50 ns and strong scalability. This work significantly enhances both scheduling accuracy and internal transparency of TSN devices, while establishing a generalizable latency characterization framework for commercial programmable hardware—providing critical enablers for large-scale Deterministic Networking deployment.

Technology Category

• Planning, Routing, and Scheduling: Scheduling
• Machine Learning: Hardware-aware ML
• Multiagent Systems: Agent-Based Simulation and Emergent Behavior

Application Category

• Systems and Infrastructure for Web, Mobile and WoT: Web performance, measurement, and characterization
• Economics, Online Markets and Human Computation: Incentives in network design for Web infrastructures and ecosystems
• Responsible Web: Human-perceived consequences of algorithmic deployment on the web

Abstract

Time-Sensitive Networking (TSN) is a set of IEEE standards that extends Ethernet with real-time capabilities. Among its mechanisms, TSN can coordinate transmission times network-wide to minimize queueing, ensuring low latency and bounded delay. This coordination is computed offline and yields a network-wide schedule. The Time-Aware Shaper (TAS), implemented in TSN bridges, protects high-priority scheduled traffic from lower-priority (best-effort) flows by periodically opening and closing priority queues according to this schedule. Deterministic Networking (DetNet), standardized by the IETF, provides similar guarantees at Layer 3 and can leverage TSN mechanisms such as TAS for that purpose. Commercially available TSN-capable switches typically implement TAS in hardware but rarely disclose internal processing delays such as queue opening latency. Such information is essential for precise scheduling but largely unavailable to system designers. In this work, we present P4-TAS, a P4-based implementation of the TAS on a hardware switching ASIC. Our design introduces a novel approach for periodic queue control using a continuous stream of internally generated TAS control frames. We identify and quantify three sources of internal delay on a nanosecond scale which also exist in other implementations that directly affect the precision of executed schedules, providing transparency for future implementations and scheduling algorithms. Moreover, we provide an MPLS/TSN translation layer that enables P4-TAS to operate within DetNet environments, allowing TSN time-based traffic shaping to be carried over high-speed 400 Gb/s forwarding. Finally, we evaluate the scalability of P4-TAS and compare it to available TAS implementations.

Problem

• Implementing Time-Aware Shaper with precise queue control in P4
• Quantifying internal delays affecting schedule precision in TSN switches
• Enabling TSN time-based traffic shaping in high-speed DetNet environments

Innovation

• P4-based hardware implementation of Time-Aware Shaper
• Uses internally generated control frames for queue management
• Provides MPLS/TSN translation for DetNet integration