An MLIR pipeline for offloading Fortran to FPGAs via OpenMP

2025-11-11

Proceedings of the SC '25 Workshops of the International Conference for High Performance Computing, Networking, Storage and Analysis

AI Summary

Efficiently offloading Fortran applications—widely used in high-performance computing (HPC)—onto FPGAs remains challenging due to limited compiler support for heterogeneous programming and hardware-specific optimization. Method: This paper proposes an MLIR-based, OpenMP directive-driven compilation framework. It employs Flang as the Fortran frontend and integrates OpenMP and high-level synthesis (HLS) dialects within MLIR to establish an end-to-end compilation pipeline—from standard OpenMP target directives to FPGA-executable bitstreams. Contribution/Results: To our knowledge, this is the first MLIR-based approach enabling selective FPGA offloading for Fortran, supporting manual kernel optimization and fine-grained directive-level control. Leveraging MLIR’s modular infrastructure, the framework ensures flexible reuse and extensibility of compilation components. Experimental evaluation demonstrates substantial improvements in cross-platform programmability, developer productivity, and hardware mapping flexibility. The results validate MLIR’s feasibility and superiority as a unified intermediate representation for FPGA-accelerated compiler design.

Technology Category

• Machine Learning: Hardware-aware ML
• Natural Language Processing: Code Generation / Program Synthesis from Natural Language
• Knowledge Representation and Reasoning: Logic Programming

Application Category

• Systems and Infrastructure for Web, Mobile and WoT: Applied ML and AI for Web-based mobile applications
• User Modeling, Personalization and Recommendation: Federated recommendation systems and personalization
• Security and Privacy: Security and privacy of machine learning and AI applications

Abstract

With the slowing of Moore's Law, heterogeneous computing platforms such as Field Programmable Gate Arrays (FPGAs) have gained increasing interest for accelerating HPC workloads. In this work we present, to the best of our knowledge, the first implementation of selective code offloading to FPGAs via the OpenMP target directive within MLIR. Our approach combines the MLIR OpenMP dialect with a High-Level Synthesis (HLS) dialect to provide a portable compilation flow targeting FPGAs. Unlike prior OpenMP FPGA efforts that rely on custom compilers, by contrast we integrate with MLIR and so support any MLIR-compatible front end, demonstrated here with Flang. Building upon a range of existing MLIR building blocks significantly reduces the effort required and demonstrates the composability benefits of the MLIR ecosystem. Our approach supports manual optimisation of offloaded kernels through standard OpenMP directives, and this work establishes a flexible and extensible path for directive-based FPGA acceleration integrated within the MLIR ecosystem.

Problem

• Developing MLIR pipeline for FPGA offloading via OpenMP
• Enabling portable compilation flow using HLS dialect
• Supporting directive-based FPGA acceleration in MLIR ecosystem

Innovation

• OpenMP target directive offloading to FPGAs
• MLIR OpenMP dialect combined with HLS dialect
• Portable compilation flow supporting MLIR-compatible front ends