🤖 AI Summary
This work addresses the semantic gap between natural language specifications and RTL designs, which often leads to SystemVerilog assertions containing syntactic errors or semantic inaccuracies that hinder formal verification. To bridge this gap, the authors propose a knowledge graph–based multi-agent collaborative framework that unifies specifications, RTL code, and verification feedback into a structured intermediate representation for the first time. This enables traceable, design-anchored contextual modeling and supports a closed-loop assertion refinement process through a triple iterative optimization mechanism—comprising syntax repair, counterexample-guided correction, and coverage-driven enhancement. Evaluated on seven benchmark designs, the generated assertions are all compilable with low syntax-repair overhead and achieve formal verification coverage ranging from 78.5% to 99.4%.
📝 Abstract
Recent advances in Large Language Models (LLMs) have enabled workflows that generate SystemVerilog Assertions (SVAs) from natural-language specifications, with the potential to accelerate Formal Verification (FV). However, high-quality assertion synthesis remains challenging because specifications are often ambiguous or incomplete and critical micro-architectural details reside in the Register Transfer Level (RTL). Many existing approaches treat the specification and RTL as loosely structured text, which weakens specification-to-RTL grounding and leads to semantic mismatches and frequent syntax failures during formal parsing and elaboration. This work addresses these limitations with a verification-centric Knowledge Graph (KG) constructed from structured Intermediate Representations (IRs) extracted from the specification, RTL, and formal-tool feedback, including syntax diagnostics, Counterexamples (CEXs), and coverage reports. The KG links requirements, design hierarchy, signals, assumptions, and properties to provide traceable, design-grounded context for generation. A multi-agent workflow queries and updates this KG to generate SVAs and to drive three refinement loops: syntax repair guided by tool diagnostics, CEX-guided correction using trace links, and coverage-directed property augmentation. Evaluation across seven benchmark designs indicates that KG-based context retrieval improves specification-to-RTL grounding and consistently produces compilable SVAs with low syntax-repair overhead. The approach achieves formal coverage ranging from 78.5% to 99.4%, though convergence exhibits design dependence with complex temporal and arithmetic reasoning remaining challenging for current LLM capabilities.