Chip Floorplanning Combining Convex and Non-convex Optimization

2026-07-23

AI Summary

This work addresses the challenge of minimizing wirelength while resolving module overlaps in VLSI floorplanning by proposing a three-stage fixed-outline placement framework that synergistically integrates non-convex and convex optimization techniques. The approach begins with a quadratic placement to generate a topology-aware initial solution, followed by a joint optimization of wirelength and overlap using an Adam-based projected gradient method. Finally, legalization is efficiently achieved through a logarithmic barrier convex model derived from horizontal and vertical constraint graphs. This framework represents the first unified placement flow that cohesively combines non-convex and convex optimization within a single pipeline, significantly enhancing wirelength quality. Experimental results on MCNC, GSRC, and HB+ benchmarks demonstrate state-of-the-art performance, with average HPWL improvements of at least 1% and 5% over existing methods.

Abstract

Floorplanning is a critical early stage of VLSI physical design, and its quality directly impacts interconnect wirelength, chip performance, and downstream design efficiency. This article presents a multi-stage fixed-outline floorplanning framework that combines non-convex and convex optimization. The framework operates in three successive phases. In the initial floorplanning phase, a quadratic placement optimizes module connectivity to produce a topology-aware starting configuration with strong net clustering, albeit with significant module overlaps. In the global floorplanning phase, Adam-based projected gradient method is employed to solve non-convex optimization that minimizes wirelength and overlap. In the legalization phase, a log-transformed model exploiting horizontal and vertical constraint graphs eliminates residual overlaps under a convex formulation. Experiments on the MCNC, GSRC and HB+ benchmarks demonstrate that the framework achieves state-of-the-art wirelength quality, reducing average HPWL by at least 1\% and 5\% compared to state-of-the-art floorplanners on tested benchmarks.

Problem

• floorplanning
• VLSI physical design
• wirelength minimization
• module overlap
• fixed-outline constraint

Innovation

• floorplanning
• convex optimization
• non-convex optimization
• quadratic placement
• constraint graphs