Demystifying FPGA Hard NoC Performance

2025-03-13

AI Summary

Hardened on-chip networks (Hard NoCs) in FPGAs lack systematic empirical evaluation. Method: This work presents the first comprehensive microarchitectural characterization of the Xilinx Versal multi-die FPGA’s Hard NoC, leveraging hardware performance counters, place-and-route analysis, and multidimensional traffic injection experiments. Contribution/Results: We quantitatively expose critical design trade-offs—including up to 2.1× inter-SLR directional interconnect performance asymmetry, suboptimal configurations generated by the NoC compiler, and the mitigation of high-frequency advantages under specific traffic patterns. Our findings enable a 30–40% reduction in inter-SLR link utilization, eliminate general-purpose logic overhead, and remove most on-chip crossbar critical paths. This study fills a fundamental gap in empirical Hard NoC research and provides essential insights for NoC-aware synthesis and mapping optimization.

Technology Category

• Machine Learning: Hardware-aware ML
• Search and Optimization: Evaluation and Analysis
• Planning, Routing, and Scheduling: Optimization of Spatio-temporal Systems

Application Category

• Systems and Infrastructure for Web, Mobile and WoT: Web performance, measurement, and characterization
• Economics, Online Markets and Human Computation: Incentives in network design for Web infrastructures and ecosystems
• Graph Algorithms and Modeling for the Web: Algorithms and analysis for incomplete, noisy, or partially observed Web-related graphs

Abstract

With the advent of modern multi-chiplet FPGA architectures, vendors have begun integrating hardened NoC to address the scalability, resource usage, and frequency disadvantages of soft NoCs. However, as this work shows, effectively harnessing these hardened NoC is not trivial. It requires detailed knowledge of the microarchitecture and how it relates to the physical design of the FPGA. Existing literature has provided in-depth analyses for NoC in MPSoC devices, but few studies have systematically evaluated hardened NoC in FPGA, which have several unique implications. This work aims to bridge this knowledge gap by demystifying the performance and design trade-offs of hardened NoC on FPGA. Our work performs detailed performance analysis of hard (and soft) NoC under different settings, including diverse NoC topologies, routing strategies, traffic patterns and different external memories under various NoC placements. In the context of Versal FPGAs, our results show that using hardened NoC in multi-SLR designs can reduce expensive cross-SLR link usage by up to 30~40%, eliminate general-purpose logic overhead, and remove most critical paths caused by large on-chip crossbars. However, under certain aggressive traffic patterns, the frequency advantage of hardened NoC is outweighed by the inefficiency in the network microarchitecture. We also observe suboptimal solutions from the NoC compiler and distinct performance variations between the vertical and horizontal interconnects, underscoring the need for careful design. These findings serve as practical guidelines for effectively integrating hardened NoC and highlight important trade-offs for future FPGA-based systems.

Problem

• Evaluates performance of hardened NoC in FPGAs.
• Analyzes trade-offs in NoC design and placement.
• Identifies inefficiencies in NoC microarchitecture under traffic.

Innovation

• Detailed performance analysis of hard NoC
• Reduced cross-SLR link usage by 30-40%
• Identified NoC compiler suboptimal solutions