A Systematic Approach for Multi-objective Double-side Clock Tree Synthesis

2025-03-16

AI Summary

Existing clock tree synthesis (CTS) methods for double-sided metal-layer integration lack systematic multi-objective optimization, particularly for post-Moore 3D integration with nanoscale through-silicon vias (nTSVs). Method: This work proposes the first unified framework integrating hierarchical clock routing, concurrent buffer and nTSV insertion, and fine-grained skew correction. It combines hierarchical structural modeling, nTSV-aware timing analysis, concurrent optimization algorithms, and iterative skew compensation to enable co-optimization of front- and back-side metal layers and timing. Contribution/Results: Compared to state-of-the-art open-source tools, our approach achieves superior performance across all key metrics—clock latency, skew, total wirelength, buffer count, and nTSV count—demonstrating the first joint optimization of latency, skew, wirelength, and device count. Experimental results validate substantial performance gains for double-sided clock trees in advanced packaging contexts.

Technology Category

• Planning, Routing, and Scheduling: Optimization of Spatio-temporal Systems
• Constraint Satisfaction and Optimization: Distributed CSP/Optimization
• Search and Optimization: Distributed Search

Application Category

• Graph Algorithms and Modeling for the Web: Algorithms and analysis for heterogeneous, signed, attributed, multi-relational, temporal, higher-order, and annotated Web-related graphs
• Systems and Infrastructure for Web, Mobile and WoT: Web performance, measurement, and characterization
• Security and Privacy: Large-scale security measurements

Abstract

As the scaling of semiconductor devices nears its limits, utilizing the back-side space of silicon has emerged as a new trend for future integrated circuits. With intense interest, several works have hacked existing backend tools to explore the potential of synthesizing double-side clock trees via nano Through-Silicon-Vias (nTSVs). However, these works lack a systematic perspective on design resource allocation and multi-objective optimization. We propose a systematic approach to design clock trees with double-side metal layers, including hierarchical clock routing, concurrent buffers and nTSVs insertion, and skew refinement. Compared with the state-of-the-art (SOTA) methods, the widely-used open-source tool, our algorithm outperforms them in latency, skew, wirelength, and the number of buffers and nTSVs.

Problem

• Systematic approach for double-side clock tree synthesis
• Optimizes design resource allocation and multi-objective goals
• Improves latency, skew, wirelength, and buffer/nTSV usage

Innovation

• Hierarchical clock routing for efficiency
• Concurrent buffers and nTSVs insertion
• Skew refinement for improved performance