Probabilistic Verification for Modular Network-on-Chip Systems (extended version)

2025-11-17

AI Summary

To address data transmission unreliability in Network-on-Chip (NoC) systems induced by power supply noise (PSN), this paper proposes a modular modeling and probabilistic verification methodology based on the Modest language. The method integrates modular router models with a hierarchical verification framework, enabling unified formal verification of functional correctness and PSN sensitivity—from individual routers up to 8×8 NoC topologies. Leveraging the Modest Toolset, we perform rigorous formal verification and statistical model checking to quantitatively assess communication consistency, functional reliability, and noise robustness. Compared to conventional approaches, our methodology significantly enhances verifiability, scalability, and model reusability at early design stages. It establishes a novel, formally grounded modeling paradigm for high-reliability NoC design under heterogeneous and dynamic traffic conditions.

Technology Category

• Planning, Routing, and Scheduling: Scheduling under Uncertainty
• Reasoning under Uncertainty: Relational Probabilistic Models
• Machine Learning: Calibration & Uncertainty Quantification

Application Category

• Graph Algorithms and Modeling for the Web: Algorithms and analysis for incomplete, noisy, or partially observed Web-related graphs
• Systems and Infrastructure for Web, Mobile and WoT: Energy management for devices in mobile Web and WoT environments
• Security and Privacy: Large-scale security measurements

Abstract

Quantitative verification can provide deep insights into reliable Network-On-Chip (NoC) designs. It is critical to understanding and mitigating operational issues caused by power supply noise (PSN) early in the design process: fluctuations in network traffic in modern NoC designs cause dramatic variations in power delivery across the network, leading to unreliability and errors in data transfers. Further complicating these challenges, NoC designs vary widely in size, usage, and implementation. This case study paper presents a principled, systematic, and modular NoC modeling approach using the Modest language that closely reflects the standard hierarchical design approach in digital systems. Using the Modest Toolset, functional and quantitative correctness was established for several NoC models, all of which were instantiated from a generic modular router model. Specifically, this work verifies the functional correctness of a generic router, inter-router communication, and the entire NoC. Statistical model checking was used to verify PSN-related properties for NoCs of size up to 8x8.

Problem

• Verifying functional correctness of modular Network-on-Chip systems
• Mitigating operational issues caused by power supply noise
• Establishing quantitative reliability for scalable NoC designs

Innovation

• Modest language for modular NoC modeling
• Statistical model checking for PSN verification
• Generic router model instantiation for scalability