Functional Interface Blocks for Neuromorphic Hardware: A Junction-Centered Framework

2026-06-02

AI Summary

This work addresses interface compatibility challenges in heterogeneous neuromorphic hardware arising from disparities in device electrical characteristics and dynamic behaviors. To resolve this, the authors propose a node-centric, systematic interface framework that organizes interconnects into standardized functional interface modules by explicitly defining driving and sensing roles. For the first time, the framework links nodal load-line conditions with reusable interface functionalities, establishing a general design paradigm for cooperative operation of heterogeneous devices. The interface primitives are implemented using second-generation current conveyors (CCIIs), and a hardware validation platform integrating memristive synapses and unijunction transistor (UJT) neurons is constructed. The efficacy of the proposed framework is successfully demonstrated through a Pavlovian conditioning task, ensuring correct and coordinated operation among heterogeneous components.

Abstract

Heterogeneous neuromorphic hardware integrates devices with dissimilar electrical characteristics and dynamics, making functional compatibility at their interconnections a primary design challenge. Direct coupling alone is insufficient to ensure correct operation, because the load-line conditions established at each junction determine the effective operating regime. Here, we propose a junction-centered interface framework in which inter-device connections are described through assigned drive/sense roles and organized into canonical functional interface blocks. As a concrete hardware realization, a second-generation current conveyor (CCII)-based implementation is then adopted as a composite realization of these interface primitives. The framework is validated experimentally in a Pavlovian-conditioning demonstrator combining a memristive synapse with a unijunction-transistor (UJT) post-neuron. By linking local junction conditions to reusable interface functions, the proposed methodology provides a systematic basis for the design and analysis of heterogeneous neuromorphic systems.

Problem

• neuromorphic hardware
• heterogeneous integration
• functional compatibility
• junction interface
• load-line conditions

Innovation

• junction-centered interface
• functional interface blocks
• neuromorphic hardware
• current conveyor (CCII)
• heterogeneous integration