CATCH: a Cost Analysis Tool for Co-optimization of chiplet-based Heterogeneous systems

2025-03-20

AI Summary

Early-stage design of chiplet-based heterogeneous systems involves complex, multidimensional trade-offs—including chiplet count, partitioning strategy, interconnect type, and packaging technology—posing significant challenges for cost-aware optimization. Method: This paper introduces CATCH, the first end-to-end cost modeling and multi-objective co-optimization framework tailored for 2.5D/3D chiplet integration, accompanied by an open-source analytical tool. The framework integrates statistical yield modeling, thermo-electro-mechanical coupled simulation, a comprehensive packaging process cost database, and multivariate sensitivity analysis to enable quantitative trade-offs among defect density, test overhead, I/O selection, and substrate fabrication technology. Contribution/Results: Case studies across multiple technology nodes demonstrate that CATCH automatically identifies optimal chiplet die sizes and stacking configurations, reducing total system cost by 18–32% and accelerating design decision-making by an order of magnitude compared to conventional approaches.

Technology Category

• Constraint Satisfaction and Optimization: Distributed CSP/Optimization
• Machine Learning: Hardware-aware ML
• Search and Optimization: Sampling/Simulation-based Search

Application Category

• Economics, Online Markets and Human Computation: Cost models of using LLMs in production systems
• Systems and Infrastructure for Web, Mobile and WoT: Web performance, measurement, and characterization
• Graph Algorithms and Modeling for the Web: Foundation models and LLMs for Web-related graphs

Abstract

With the increasing prevalence of chiplet systems in high-performance computing applications, the number of design options has increased dramatically. Instead of chips defaulting to a single die design, now there are options for 2.5D and 3D stacking along with a plethora of choices regarding configurations and processes. For chiplet-based designs, high-impact decisions such as those regarding the number of chiplets, the design partitions, the interconnect types, and other factors must be made early in the development process. In this work, we describe an open-source tool, CATCH, that can be used to guide these early design choices. We also present case studies showing some of the insights we can draw by using this tool. We look at case studies on optimal chip size, defect density, test cost, IO types, assembly processes, and substrates.

Problem

• Optimizes chiplet-based heterogeneous system designs
• Analyzes cost and performance of 2.5D/3D stacking options
• Guides early decisions on chiplets, interconnects, and configurations

Innovation

• Open-source tool for chiplet system design
• Optimizes chip size and defect density
• Analyzes test cost and assembly processes