A Unified Framework for Quantitative Cache Analysis

2025-03-20

AI Summary

This paper addresses the long-standing challenge of quantitatively analyzing non-LRU cache replacement policies—such as FIFO and MRU—under arbitrary associativity and microarchitectural timing anomalies. We propose the first unified analytical framework for this problem. Methodologically, we introduce the novel concept of *block competitiveness*, enabling systematic transfer of LRU persistence analysis to non-LRU policies, and integrate worst-case execution time (WCET) analysis techniques to overcome the infeasibility of conventional approaches under timing anomalies. Our contributions are threefold: (1) the first rigorous, block-level competitiveness modeling for FIFO and MRU; (2) high-precision quantification of cache behavior across arbitrary cache ways and timing-anomalous microarchitectures; and (3) empirical validation on the TACLeBench benchmark suite, demonstrating accuracy approaching that of LRU-based analysis while ensuring both theoretical soundness and engineering deployability.

Technology Category

• Machine Learning: Evaluation and Analysis
• Search and Optimization: Evaluation and Analysis
• Cognitive Modeling & Cognitive Systems: Analogy

Application Category

• Security and Privacy: Large-scale security measurements
• Graph Algorithms and Modeling for the Web: Algorithms and analysis for incomplete, noisy, or partially observed Web-related graphs
• Web Mining and Content Analysis: Web measurements

Abstract

In this work we unify two existing lines of work towards cache analysis for non-LRU policies. To this end, we extend the notion of competitiveness to block-wise competitiveness and systematically analyze the competitiveness and block competitiveness of FIFO and MRU relative to LRU for arbitrary associativities. We show how competitiveness and block competitiveness can be exploited in state-of-the-art WCET analysis based on the results of existing persistence analyses for LRU. Unlike prior work, our approach is applicable to microarchitectures that exhibit timing anomalies. We experimentally evaluate the precision and cost of our approach on benchmarks from TACLeBench. The experiments demonstrate that quantitative cache analysis for FIFO and MRU comes close to the precision of LRU.

Problem

• Unify cache analysis for non-LRU policies
• Extend competitiveness notions for FIFO and MRU
• Apply analysis to microarchitectures with timing anomalies

Innovation

• Extends competitiveness to block-wise analysis
• Integrates competitiveness into WCET analysis
• Applicable to timing-anomalous microarchitectures