Uncertainty Removal in Verification of Nonlinear Systems against Signal Temporal Logic via Incremental Reachability Analysis

2025-11-18

AI Summary

For uncertain continuous-time nonlinear systems, Signal Temporal Logic (STL) verification faces a fundamental challenge: ambiguous “uncertain satisfaction” due to either over-approximation of reachable sets or incomplete simulation. This paper proposes an STL verification framework based on incremental reachability analysis. Our method addresses the problem by: (1) extending STL semantics with Boolean interval arithmetic and traceable uncertainty annotations; (2) performing localized, incremental refinement only on reachable sets that induce uncertainty—avoiding costly global recomputation; and (3) introducing a hierarchical signal processing architecture enabling synchronized online/offline monitoring and adaptation to system evolution. Evaluated on a nonlinear oscillator benchmark, the approach substantially reduces satisfaction ambiguity, demonstrating high accuracy, computational efficiency, and robustness for complex nonlinear systems under uncertainty.

Technology Category

• Reasoning under Uncertainty: Uncertainty Representations
• Constraint Satisfaction and Optimization: Satisfiability Modulo Theories
• Multiagent Systems: Multiagent Systems under Uncertainty

Application Category

• Search and Retrieval-Augmented AI: Web query analysis, representation and understanding
• Graph Algorithms and Modeling for the Web: Algorithms and analysis for incomplete, noisy, or partially observed Web-related graphs
• Systems and Infrastructure for Web, Mobile and WoT: Web performance, measurement, and characterization

Abstract

A framework is presented for the verification of Signal Temporal Logic (STL) specifications over continuous-time nonlinear systems under uncertainty. Based on reachability analysis, the proposed method addresses indeterminate satisfaction caused by over-approximated reachable sets or incomplete simulations. STL semantics is extended via Boolean interval arithmetic, enabling the decomposition of satisfaction signals into unitary components with traceable uncertainty markers. These are propagated through the satisfaction tree, supporting precise identification even in nested formulas. To improve efficiency, only the reachable sets contributing to uncertainty are refined, identified through the associated markers. The framework allows online or offline monitoring to adapt to incremental system evolution while avoiding unnecessary recomputation. A case study on a nonlinear oscillator demonstrates a significant reduction in satisfaction ambiguity, highlighting the effectiveness of the approach.

Problem

• Verifying Signal Temporal Logic for nonlinear systems with uncertainty
• Resolving indeterminate satisfaction via incremental reachability analysis
• Reducing satisfaction ambiguity in continuous-time nonlinear systems

Innovation

• Incremental reachability analysis for uncertainty removal
• Boolean interval arithmetic extends STL semantics
• Refines only reachable sets contributing to uncertainty