Defect-Aware Physics-Based Compact Model for Ferroelectric nvCap: From TCAD Calibration to Circuit Co-Design

2025-11-26

AI Summary

Ferroelectric non-volatile capacitive memory promises non-destructive readout and low-power in-memory computing, yet its adoption in high-density gateless arrays and 3D-stacked architectures is hindered by narrow storage windows (1–10 fF/μm) and the absence of physics-based compact models capturing small-signal capacitance, process variability, and cycling-induced degradation. Method: This project establishes the first multi-physics compact model integrating polarization-dependent capacitance, interfacial/bulk defect dynamics, and process variations—calibrated via combined experimental and TCAD characterization—and enables cross-scale, closed-loop validation from device to circuit co-design. Contribution/Results: The model accurately captures sub-femtofarad capacitance variations and degradation mechanisms, supports ±5 mV read margin optimization, and quantifies endurance-induced circuit performance degradation. It provides a scalable, physics-informed device model foundation for 3D compute-in-memory architectures.

Technology Category

• Machine Learning: Learning on the Edge & Model Compression
• Cognitive Modeling & Cognitive Systems: (Computational) Cognitive Architectures
• Computer Vision: Learning & Optimization for CV

Application Category

• User Modeling, Personalization and Recommendation: On-Device user modeling, personalization, and recommendation
• Graph Algorithms and Modeling for the Web: Efficient manipulation of static and dynamic Web-related graphs
• Security and Privacy: Large-scale security measurements

Abstract

Ferroelectric non-volatile capacitance-based memories enable non-destructive readout and low-power in-memory computing with 3D stacking potential. However, their limited memory window (1-10 fF/μm) requires material-device-circuit co-optimization. Existing compact models fail to capture the physics of small-signal capacitance, device variability, and cycling degradation, which are critical parameters for circuit design. In non-volatile capacitance devices, the small-signal capacitance difference of the polarization states is the key metric. The majority of the reported compact models do not incorporate any physical model of the capacitance as a function of voltage and polarization. We present a physics-based compact model that captures small-signal capacitance, interface and bulk defect contributions, and device variations through multi-scale modeling combining experimental data, TCAD simulations, and circuit validation. Based on this methodology, we show optimized memory read-out with +/- 5 mV sense margin and impact of device endurance at the circuit level. This work presents a comprehensive compact model which enables the design of selector-less arrays and 3D-stacked memories for compute-in-memory and storage memory.

Problem

• Modeling small-signal capacitance in ferroelectric non-volatile memories
• Capturing device variability and cycling degradation effects
• Enabling material-device-circuit co-design for 3D stacked memories

Innovation

• Physics-based compact model captures small-signal capacitance
• Incorporates defect contributions and device variations
• Enables selector-less arrays and 3D-stacked memories