Dual-Issue Execution of Mixed Integer and Floating-Point Workloads on Energy-Efficient In-Order RISC-V Cores

2025-03-26

AI Summary

To address the inefficiency of single-issue in-order RISC-V cores in energy-constrained scenarios when executing integer–floating-point mixed workloads, this paper proposes COPIFT—a methodology and accompanying RISC-V instruction set extension enabling a low-cost, highly flexible dual-issue microarchitecture. By extending the ISA to support parallel issuance of heterogeneous instructions and designing a coordinated scheduling mechanism between integer and floating-point pipelines, COPIFT overcomes the single-issue bottleneck without significant area or power overhead. Evaluated against the RV32G baseline, it achieves a 1.47× average IPC improvement, a peak IPC of 1.75, and a 1.37× reduction in energy consumption. Its core contribution is the first low-overhead dual-issue design for in-order RISC-V cores—uniquely balancing energy efficiency, silicon area, and general-purpose programmability—thereby establishing a new paradigm for mixed-precision computing at the edge.

Technology Category

• Machine Learning: Hardware-aware ML
• Constraint Satisfaction and Optimization: Mixed Discrete/Continuous Optimization
• Planning, Routing, and Scheduling: Mixed Discrete/Continuous Planning

Application Category

• Systems and Infrastructure for Web, Mobile and WoT: Energy management for devices in mobile Web and WoT environments
• Responsible Web: Data and user privacy-enhancing technologies for the Web
• Security and Privacy: Large-scale security measurements

Abstract

To meet the computational requirements of modern workloads under tight energy constraints, general-purpose accelerator architectures have to integrate an ever-increasing number of extremely area- and energy-efficient processing elements (PEs). In this context, single-issue in-order cores are commonplace, but lean dual-issue cores could boost PE IPC, especially for the common case of mixed integer and floating-point workloads. We develop the COPIFT methodology and RISC-V ISA extensions to enable low-cost and flexible dual-issue execution of mixed integer and floating-point instruction sequences. On such kernels, our methodology achieves speedups of 1.47x, reaching a peak 1.75 instructions per cycle, and 1.37x energy improvements on average, over optimized RV32G baselines.

Problem

• Enhance dual-issue execution for mixed workloads
• Improve energy efficiency in RISC-V cores
• Boost IPC for integer and floating-point operations

Innovation

• Dual-issue execution for mixed workloads
• RISC-V ISA extensions for flexibility
• Energy-efficient in-order core design