NL2GDS: LLM-aided interface for Open Source Chip Design

2026-03-05

AI Summary

This work proposes the first end-to-end automated framework that translates natural language specifications directly into GDSII layouts, addressing the slow pace of hardware prototyping caused by the gap between high-level specifications and register-transfer level (RTL) implementations. The framework leverages a multi-engine large language model to generate and verify synthesizable HDL code, which is then automatically synthesized, placed, and routed through the open-source OpenLane physical design flow. Evaluated on the ISCAS’85/89 benchmark suites, the approach achieves up to 36% reduction in area, 35% lower delay, and 70% power savings compared to baseline designs. By significantly lowering the barrier to ASIC design, this framework advances the democratization of hardware development.

Technology Category

• Machine Learning: Hardware-aware ML
• Natural Language Processing: Code Generation / Program Synthesis from Natural Language
• Humans and AI: AI for Accessibility

Application Category

• Systems and Infrastructure for Web, Mobile and WoT: Applied ML and AI for Web-based mobile applications
• Economics, Online Markets and Human Computation: Cost models of using LLMs in production systems
• Graph Algorithms and Modeling for the Web: Foundation models and LLMs for Web-related graphs

Abstract

The growing complexity of hardware design and the widening gap between high-level specifications and register-transfer level (RTL) implementation hinder rapid prototyping and system design. We introduce NL2GDS (Natural Language to Layout), a novel framework that leverages large language models (LLMs) to translate natural language hardware descriptions into synthesizable RTL and complete GDSII layouts via the open-source OpenLane ASIC flow. NL2GDS employs a modular pipeline that captures informal design intent, generates HDL using multiple LLM engines and verifies them, and orchestrates automated synthesis and layout. Evaluations on ISCAS'85 and ISCAS'89 benchmark designs demonstrate up to 36% area reduction, 35% delay reduction, and 70% power savings compared to baseline designs, highlighting its potential to democratize ASIC design and accelerate hardware innovation.

Problem

• hardware design
• RTL implementation
• design abstraction gap
• rapid prototyping
• ASIC design

Innovation

• NL2GDS
• Large Language Models (LLMs)
• Natural Language to RTL
• Open-Source ASIC Design
• Automated Chip Synthesis