From RISC-V Cores to Neuromorphic Arrays: A Tutorial on Building Scalable Digital Neuromorphic Processors

2025-11-27

AI Summary

Emerging edge-AI applications demand ultra-low-power, always-on neuromorphic computing. Method: This paper proposes a progressive architectural design methodology for scalable digital neuromorphic processors, instantiated in the SENECO platform. Starting from a RISC-V core array, the architecture incrementally evolves into a heterogeneous system integrating domain-specific neural processing units (NPUs), loop controllers, and event-driven execution. Key techniques include spike-event grouping, depth-first convolution scheduling, hardware-accelerated attention, and a custom network-on-chip (NoC). Contribution/Results: The work systematically synthesizes architecture–algorithm–software co-design insights, yielding a reusable brain-inspired processor paradigm, sparse activation mapping strategy, and energy-efficiency optimization pathway. It achieves significant improvements in spiking neural network (SNN) inference energy efficiency while preserving programmability and functional generality.

Technology Category

• Machine Learning: Hardware-aware ML
• Cognitive Modeling & Cognitive Systems: Neural Spike Coding
• Humans and AI: Brain-Sensing and Analysis

Application Category

• Economics, Online Markets and Human Computation: Incentives in network design for Web infrastructures and ecosystems
• Systems and Infrastructure for Web, Mobile and WoT: Applied ML and AI for Web-based mobile applications
• Graph Algorithms and Modeling for the Web: Graph neural networks and deep learning approaches for Web-related graphs

Abstract

Digital neuromorphic processors are emerging as a promising computing substrate for low-power, always-on EdgeAI applications. In this tutorial paper, we outline the main architectural design principles behind fully digital neuromorphic processors and illustrate them using the SENECA platform as a running example. Starting from a flexible array of tiny RISC-V processing cores connected by a simple Network-on-Chip (NoC), we show how to progressively evolve the architecture: from a baseline event-driven implementation of fully connected networks, to versions with dedicated Neural Processing Elements (NPEs) and a loop controller that offloads fine-grained control from the general-purpose cores. Along the way, we discuss software and mapping techniques such as spike grouping, event-driven depth-first convolution for convolutional networks, and hard-attention style processing for high-resolution event-based vision. The focus is on architectural trade-offs, performance and energy bottlenecks, and on leveraging flexibility to incrementally add domain-specific acceleration. This paper assumes familiarity with basic neuromorphic concepts (spikes, event-driven computation, sparse activation) and deep neural network workloads. It does not present new experimental results; instead, it synthesizes and contextualizes findings previously reported in our SENECA publications to provide a coherent, step-by-step architectural perspective for students and practitioners who wish to design their own digital neuromorphic processors.

Problem

• Design scalable digital neuromorphic processors for EdgeAI applications
• Evolve architecture from RISC-V cores to specialized neural processing elements
• Address trade-offs in performance, energy, and domain-specific acceleration

Innovation

• Start with RISC-V cores and NoC for flexibility
• Add Neural Processing Elements and loop controller
• Use spike grouping and event-driven convolution techniques