Mapping Code on Coarse Grained Reconfigurable Arrays Using a SAT Solver

2025-12-02

Euro-Par Workshops

AI Summary

Addressing the challenges of computationally expensive compilation and difficulty in determining the minimum initiation interval (II) for loop mapping on coarse-grained reconfigurable arrays (CGRAs), this paper proposes a SAT-based formal compilation optimization method. The core contribution is the Kernel Mobility Schedule—a novel scheduling mechanism that uniformly encodes all valid dataflow graph (DFG) mappings onto the target CGRA topology as a Boolean satisfiability (SAT) problem. It jointly models architectural constraints—including resource availability, interconnect connectivity, and timing—and modulo scheduling semantics to enable II-driven, end-to-end mapping search. Experimental evaluation demonstrates that our approach reduces average compilation time by 37% while achieving a 12.6% smaller II and higher mapping quality, significantly outperforming state-of-the-art methods.

Technology Category

• Constraint Satisfaction and Optimization: Satisfiability
• Planning, Routing, and Scheduling: Optimization of Spatio-temporal Systems
• Search and Optimization: Sampling/Simulation-based Search

Application Category

• Graph Algorithms and Modeling for the Web: Efficient manipulation of static and dynamic Web-related graphs
• Search and Retrieval-Augmented AI: Web learning to rank, online learning, and counterfactual learning for ranking
• Semantics and Knowledge: Scalable techniques for the creation, curation, publication, maintenance, and consumption of large, Web-based, structured, reusable, knowledge graphs and ontologies

Abstract

Emerging low-powered architectures like Coarse-Grain Reconfigurable Arrays (CGRAs) are becoming more common. Often included as co-processors, they are used to accelerate compute-intensive workloads like loops. The speedup obtained is defined by the hardware design of the accelerator and by the quality of the compilation. State of the art (SoA) compilation techniques leverage modulo scheduling to minimize the Iteration Interval (II), exploit the architecture parallelism and, consequentially, reduce the execution time of the accelerated workload. In our work, we focus on improving the compilation process by finding the lowest II for any given topology, through a satisfiability (SAT) formulation of the mapping problem. We introduce a novel schedule, called Kernel Mobility Schedule, to encode all the possible mappings for a given Data Flow Graph (DFG) and for a given II. The schedule is used together with the CGRA architectural information to generate all the constraints necessary to find a valid mapping. Experimental results demonstrate that our method not only reduces compilation time on average but also achieves higher quality mappings compared to existing SoA techniques.

Problem

• Mapping code onto Coarse Grained Reconfigurable Arrays (CGRAs) using SAT solvers
• Finding the lowest Iteration Interval (II) for any CGRA topology via SAT formulation
• Improving compilation time and mapping quality for CGRA-based accelerators

Innovation

• SAT solver formulation for mapping problem
• Kernel Mobility Schedule encoding possible mappings
• Generating constraints from CGRA architectural information