FREESS: A Web-Based Educational Simulator for a RISC-V-Inspired Superscalar Processor with Tomasulo-Style Dynamic Scheduling

2026-05-26

AI Summary

This work addresses the challenge of intuitively illustrating instruction-level parallelism and dynamic scheduling in superscalar processors, which existing educational tools struggle to convey effectively. To bridge this gap, the authors design and implement an open-source web-based educational simulator grounded in the RISC-V architecture and employing Tomasulo-style dynamic scheduling. The simulator provides cycle-by-cycle visualization of key microarchitectural processes—including register renaming, instruction issue, execution, write-back, commit, and memory ordering—and innovatively integrates core structures such as the reorder buffer and load/store queues into a unified textual view. It further supports flexible configuration of functional unit latencies and other microarchitectural parameters. Deployed for nearly fifteen years in advanced computer architecture courses, the tool has demonstrably enhanced students’ comprehension of complex pipeline mechanisms, and its source code is publicly available on GitHub.

Abstract

FREESS (Free Educational Superscalar Simulator) is an open-source teaching environment for instruction-level parallelism in a RISC-V-inspired superscalar processor. It provides a compact, cycle-by-cycle view of register renaming, issue, execution, write-back, commit, and memory ordering in a Tomasulo-style machine. The simulator exposes the register map, free pool, instruction window, reorder buffer, and load/store queues in one textual representation, so the evolution of the hardware state can be followed on screen and reproduced on paper. Runtime parameters such as issue width, queue sizes, and functional-unit latencies can be changed easily, enabling direct comparison among alternative superscalar organizations. The tool has supported Advanced Computer Architecture teaching for about fifteen years and is publicly available on GitHub.

Problem

• superscalar processor
• instruction-level parallelism
• Tomasulo algorithm
• RISC-V
• computer architecture education

Innovation

• superscalar processor
• Tomasulo algorithm
• instruction-level parallelism
• RISC-V
• educational simulator