Linear Complexity Fermionic Simulation on Quantum Devices with Hardware Connectivity Constraints

2026-05-30

AI Summary

This work addresses the challenge of inefficient quantum compilation for fermionic systems under constrained hardware connectivity, where existing methods suffer from super-quartic growth in gate count and circuit depth. The authors propose Accordion, an end-to-end framework that jointly optimizes fermion-to-qubit mapping, circuit synthesis, and hardware-aware routing. By fixing the Jordan-Wigner mapping to exploit its structural regularity and integrating Pauli operator analysis, Accordion achieves O(N⁴) scaling in both gate count and circuit depth for full-rank, fully connected electronic structure Hamiltonians. Evaluated on linear, IBM heavy-hex, and square-grid topologies, the method approaches information-theoretic lower bounds, reducing gate count and circuit depth by up to 79% and 77%, respectively, compared to the best baseline approaches.

Abstract

Simulating fermionic systems on quantum hardware requires compiling fermionic Hamiltonians into executable quantum circuits. Existing approaches treat each compilation stage independently, applying heuristics with localized objectives that produce circuits with superquartic gate count and depth scaling and compilation times reaching several hours for large instances. We present Accordion, an end-to-end framework that co-designs the fermion-to-qubit mapping with circuit synthesis and hardware routing. Accordion fixes the Jordan Wigner mapping, which despite its higher Pauli weight produces Pauli operators with structural regularity that enables provably efficient circuit generation. For full-rank all-to-all electronic structure Hamiltonians, we prove O(N^4) gate count and circuit depth, matching the information-theoretic lower bound imposed by the Theta(N^4) second excitation terms. On linear, IBM heavy-hex, and square-grid architectures, Accordion reduces gate count by up to 79% and circuit depth by up to 77% relative to the best baseline.

Problem

• fermionic simulation
• quantum compilation
• hardware connectivity constraints
• circuit depth
• gate count

Innovation

• fermionic simulation
• quantum circuit compilation
• Jordan-Wigner mapping
• hardware-aware synthesis
• linear complexity