🤖 AI Summary
This work addresses thermal–electrical performance degradation induced by process variations in 3.5D heterogeneous integration by introducing XRM-SSD V24/V7.0, a physics-aware predictive firmware scheduling layer that enables hardware–software co-optimization. Prior to tape-out, it dynamically regulates PowerVia voltage rails through a workload-density-driven thermal pre-hinting mechanism. For the first time, forward-looking thermal hints are integrated with multi-die interconnect architectures and extended to multi-tile systems, establishing an N×N thermal coupling matrix and a bipolar core model. Leveraging electro-thermal co-simulation, Monte Carlo process variation analysis, and a large-scale LLM inference workload dataset (90,000 timesteps), the approach achieves a thermal load correlation coefficient of R² = 0.9911, reduces compensated CPO spectral drift to below 0.36 nm, limits HBM leakage current to under 1 MB/hr, and is projected to unlock 20–30% additional compute capacity while reducing EDA guardbands by 65–68%.
📝 Abstract
This paper presents a pre-silicon analysis of XRM-SSD V24/V7.0, a physics-aware predictive firmware scheduling layer for Intel's 3.5D heterogeneous integrated packages (Foveros Direct 3D + PowerVia + EMIB-T + UCIe + HBM5). Using detailed thermal-electrical co-simulation over a 90,000-step LLM inference dataset, we show that proactive workload-density-driven thermal hinting (20-50 ms look-ahead) enables pre-positioning of PowerVia voltage rails. Key results include a thermal-load correlation of R^2 = 0.9911, compensated CPO spectral drift below 0.36 nm (21% of TSMC tolerance budget), and HBM leakage current clamped below 1 MB/hr across all load states. Monte Carlo analysis (N=2,000 trials) confirms robustness under process variation. V7.0 extends the framework to multi-tile architectures with an N x N thermal coupling matrix and two-pole kernel. The approach demonstrates potential for 20-30% released compute and 65-68% EDA guard-band reduction. All metrics are engineering projections from pre-silicon characterization. Silicon validation on Intel 18A platforms is pending. This work highlights firmware-hardware co-optimization as an effective approach to mitigating physical limits in advanced 3.5D packaging.