SAILOR: A Scalable and Energy-Efficient Ultra-Lightweight RISC-V for IoT Security

📅 2026-02-27
📈 Citations: 0
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🤖 AI Summary
This work addresses the challenge of achieving an optimal balance among area, energy efficiency, and security in existing RISC-V cores for IoT applications, where integrating cryptographic capabilities often incurs excessive hardware overhead. To this end, we propose SAILOR—a modular, scalable family of ultra-lightweight RISC-V cores featuring native support for the RISC-V Cryptography Extension and configurable serial datapaths ranging from 1 to 32 bits. By co-optimizing hardware architecture and cryptographic computation, SAILOR achieves highly efficient secure processing with minimal area overhead, effectively breaking the traditional trade-off among performance, energy efficiency, and security. Experimental results demonstrate that SAILOR improves energy efficiency by up to 13× and reduces area by as much as 59% compared to state-of-the-art solutions, while maintaining competitive computational performance.

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📝 Abstract
Recently, RISC-V has contributed to the development of IoT devices, requiring architectures that balance energy efficiency, compact area, and integrated security. However, most recent RISC-V cores for IoT prioritize either area footprint or energy efficiency, while adding cryptographic support further compromises compactness. As a result, truly integrated architectures that simultaneously optimize efficiency and security remain largely unexplored, leaving constrained IoT environments vulnerable to performance and security trade-offs. In this paper, we introduce SAILOR, an energy-efficient and scalable ultra-lightweight RISC-V core family for cryptographic applications in IoT. Our design is modular and spans 1-, 2-, 4-, 8-, 16-, and 32-bit serialized execution data-paths, prioritizing minimal area. This modular design and adaptable data-path minimizes the overhead of integrating RISC-V cryptography extensions, achieving low hardware cost while significantly improving energy efficiency. We validate our design approach through a comprehensive analysis of area, energy, and efficiency trade-offs. The results surpass state-of-the-art solutions in both performance and energy efficiency by up to 13x and reduce area by up to 59 %, demonstrating that lightweight cryptographic features can be added without prohibitive overhead, and that energy- or area-efficient designs need not compromise performance.
Problem

Research questions and friction points this paper is trying to address.

RISC-V
IoT security
energy efficiency
ultra-lightweight
cryptographic integration
Innovation

Methods, ideas, or system contributions that make the work stand out.

RISC-V
ultra-lightweight
modular architecture
energy efficiency
IoT security
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