Shifting in-DRAM

2026-02-27

AI Summary

This work addresses the limitations of existing processing-in-memory (PIM) architectures, where bit-shift operations rely on dedicated shift circuits or vertical data layouts, incurring additional overhead and compatibility issues. The authors propose a novel DRAM subarray architecture that introduces migration cell rows at both the top and bottom of the subarray within an open-bitline structure, enabling arbitrary bidirectional intra-row bit shifts under a horizontal data layout for the first time—without requiring data transposition or complex additional circuitry. The design maintains full compatibility with standard DRAM operations. Comprehensive validation through subarray reconfiguration, NVMain-based timing and energy analysis, LTSPICE circuit simulations, and Cadence Virtuoso layout implementation demonstrates the approach’s functional correctness, low overhead, and high energy efficiency, offering robust support for PIM applications such as multiplication and cryptography.

Technology Category

• Machine Learning: Hardware-aware ML
• Data Mining & Knowledge Management: Scalability, Parallel & Distributed Systems
• Search and Optimization: Distributed Search

Application Category

• Systems and Infrastructure for Web, Mobile and WoT: Data management and stream processing for Web, mobile and wireless applications
• Graph Algorithms and Modeling for the Web: Efficient manipulation of static and dynamic Web-related graphs
• Search and Retrieval-Augmented AI: Vertical and domain-specific search

Abstract

Processing-in-Memory (PIM) architectures enable computation directly within DRAM and help combat the memory wall problem. Bit-shifting is a fundamental operation that enables PIM applications such as shift-and-add multiplication, adders using carry propagation, and Galois field arithmetic used in cryptography algorithms like AES and Reed-Solomon error correction codes. Existing approaches to in-DRAM shifting require adding dedicated shifter circuits beneath the sense amplifiers to enable horizontal data movement across adjacent bitlines or vertical data layouts which store operand bits along a bitline to implement shifts as row-copy operations. In this paper, we propose a novel DRAM subarray design that enables in-DRAM bit-shifting for open-bitline architectures. In this new design, we built upon prior work that introduced a new type of cell used for row migration in asymmetric subarrays, called a"migration cell". We repurpose and extend the functionality by adding a row of migration cells at the top and bottom of each subarray which enables bidirectional bit-shifting within any given row. This new design maintains compatibility with standard DRAM operations. Unlike previous approaches to shifting, our design operates on horizontally-stored data, eliminating the need and overhead of data transposition, and our design leverages the existing cell structures, eliminating the need for additional complex logic and circuitry. We present an evaluation of our design that includes timing and energy analysis using NVMain, circuit-level validation of the in-DRAM shift operation using LTSPICE, and a VLSI layout implementation in Cadence Virtuoso.

Problem

• Processing-in-Memory
• bit-shifting
• DRAM
• memory wall
• in-DRAM computation

Innovation

• Processing-in-Memory
• in-DRAM shifting
• migration cell
• open-bitline DRAM
• bit-shifting