🤖 AI Summary
Existing hardware synthesis approaches decouple implementation selection from scheduling, failing to fully exploit FPGA heterogeneity and yielding suboptimal designs. This paper proposes the first holistic synthesis framework that jointly optimizes implementation selection and scheduling. It employs an e-graph to uniformly model algebraic transformations and hardware implementation decisions, leverages equivalence saturation for efficient exploration of multiple implementation paths, and performs timing-constrained scheduling via a primary mixed-integer linear programming (MILP) formulation augmented by ASAP-based heuristics. Evaluated on Xilinx Kintex UltraScale+ FPGAs, the method achieves an average speedup of 3.01× over Vitis HLS, with up to 5.22× acceleration for complex expressions. This work represents the first systematic breakthrough in hardware synthesis enabling end-to-end co-optimization of implementation and scheduling.
📝 Abstract
Hardware synthesis from high-level descriptions remains fundamentally limited by the sequential optimization of interdependent design decisions. Current methodologies, including state-of-the-art high-level synthesis (HLS) tools, artificially separate implementation selection from scheduling, leading to suboptimal designs that cannot fully exploit modern FPGA heterogeneous architectures. Implementation selection is typically performed by ad-hoc pattern matching on operations, a process that does not consider the impact on scheduling. Subsequently, scheduling algorithms operate on fixed selection solutions with inaccurate delay estimates, which misses critical optimization opportunities from appropriately configured FPGA blocks like DSP slices. We present SkyEgg, a novel hardware synthesis framework that jointly optimizes implementation selection and scheduling using the e-graph data structure. Our key insight is that both algebraic transformations and hardware implementation choices can be uniformly represented as rewrite rules within an e-graph, modeling the complete design space of implementation candidates to be selected and scheduled together. First, SkyEgg constructs an e-graph from the input program. It then applies both algebraic and implementation rewrites through equality saturation. Finally, it formulates the joint optimization as a mixed-integer linear programming (MILP) problem on the saturated e-graph. We provide both exact MILP solving and an efficient ASAP heuristic for scalable synthesis. Our evaluation on benchmarks from diverse applications targeting Xilinx Kintex UltraScale+ FPGAs demonstrates that SkyEgg achieves an average speedup of 3.01x over Vitis HLS, with improvements up to 5.22x for complex expressions.