A 14ns-Latency 9Gb/s 0.44mm$^2$ 62pJ/b Short-Blocklength LDPC Decoder ASIC in 22FDX

2025-12-19

AI Summary

In 5G URLLC scenarios, conventional short-length LDPC codes (e.g., N=128) under message-passing (MP) decoding exhibit inferior error-rate performance compared to polar codes, while successive-cancellation list (SCL) decoders suffer from high latency and poor area efficiency. To address these limitations, this work proposes the first multi-rate binary LDPC code of blocklength N=128 and its fully parallel MP decoder ASIC. Leveraging a customized parity-check matrix design, implementation in 22FDX FD-SOI technology, and low-power circuit optimizations, the decoder supports code rates from 1/4 to 1/2, achieving an end-to-end latency of 14 ns, an ultra-compact die area of 0.44 mm², an information throughput of 9 Gb/s, and an energy efficiency of 62 pJ/b. These metrics significantly surpass those of 5G-standard LDPC decoders, thereby simultaneously satisfying URLLC’s stringent requirements on ultra-low latency and high integration density.

Technology Category

• Machine Learning: Hardware-aware ML
• Natural Language Processing: Learning & Optimization for NLP
• Cognitive Modeling & Cognitive Systems: Neural Spike Coding

Application Category

• Security and Privacy: Large-scale security measurements
• Search and Retrieval-Augmented AI: Large language models for search
• Systems and Infrastructure for Web, Mobile and WoT: Applied ML and AI for Web-based mobile applications

Abstract

Ultra-reliable low latency communication (URLLC) is a key part of 5G wireless systems. Achieving low latency necessitates codes with short blocklengths for which polar codes with successive cancellation list (SCL) decoding typically outperform message-passing (MP)-based decoding of low-density parity-check (LDPC) codes. However, SCL decoders are known to exhibit high latency and poor area efficiency. In this paper, we propose a new short-blocklength multi-rate binary LDPC code that outperforms the 5G-LDPC code for the same blocklength and is suitable for URLLC applications using fully parallel MP. To demonstrate our code's efficacy, we present a 0.44mm$^2$ GlobalFoundries 22FDX LDPC decoder ASIC which supports three rates and achieves the lowest-in-class decoding latency of 14ns while reaching an information throughput of 9Gb/s at 62pJ/b energy efficiency for a rate-1/2 code with 128-bit blocklength.

Problem

• Designing low-latency LDPC decoders for 5G URLLC
• Overcoming high latency and area inefficiency in SCL decoders
• Achieving high throughput and energy efficiency in short-blocklength codes

Innovation

• Fully parallel message-passing LDPC decoder design
• Multi-rate binary LDPC code for short blocklengths
• 14ns latency ASIC with 9Gb/s throughput efficiency