Extension of ACETONE C code generator for multi-core architectures

2026-03-02

AI Summary

This work extends ACETONE, originally limited to generating sequential C code, to support multicore parallel code generation, thereby unlocking the parallel performance potential of multicore embedded platforms. By formally modeling the processor allocation problem, designing a scheduling heuristic, and introducing customized synchronization mechanism templates, the approach enables efficient mapping and execution of neural network layers across multicore architectures. The framework also integrates worst-case execution time (WCET) analysis, offering a predictable, efficient, and verifiable deployment solution for deep learning in safety-critical systems.

Technology Category

• Machine Learning: Hardware-aware ML
• Natural Language Processing: Code Generation / Program Synthesis from Natural Language
• Cognitive Modeling & Cognitive Systems: Neural Spike Coding

Application Category

• Systems and Infrastructure for Web, Mobile and WoT: Applied ML and AI for Web-based mobile applications
• Graph Algorithms and Modeling for the Web: Graph neural networks and deep learning approaches for Web-related graphs
• Responsible Web: Human-perceived consequences of algorithmic deployment on the web

Abstract

As the industry's interest in machine learning has grown in recent years, some solutions have emerged to safely embed them in safety-critical systems, such as the C code generator ACETONE. However, this framework is limited to generating sequential code, which cannot make most of the multi-core architectures. In this paper, we initiate an extension of ACETONE for the generation of parallel code by formally defining our processor assignment problem and surveying the state of the art on existing solutions. In the final paper, we will introduce the completed extension, including the implementation of the scheduling heuristic, the creation of templates implementing synchronization mechanisms, and an evaluation of the worst-case execution time of the framework's layers.

Problem

• multi-core architectures
• parallel code generation
• ACETONE
• code generator
• processor assignment

Innovation

• parallel code generation
• multi-core architectures
• scheduling heuristic
• synchronization mechanisms
• worst-case execution time