LOCO: A Low-Cost SNU-Self-Resilient Latch Using an Output-Split C-Element

2025-12-22

AI Summary

Radiation-induced soft errors in nanoscale CMOS circuits are increasingly severe; conventional filtering techniques protect only input nodes, necessitating additional output-side hardening that incurs substantial area and power overhead. To address this, we propose the Output-Split C-element (OSC), the first design enabling coordinated hardening at both input and output terminals. Integrating OSC with clock gating and a high-speed path, we develop LOCO—a single-node upset (SNU) self-recovering latch. Compared to state-of-the-art SNU-hardened latches, LOCO reduces transistor count by 19%, power consumption by 63.58%, delay by 74%, and power-delay product (PDP) by 92%, while significantly enhancing PVT robustness.

Technology Category

• Machine Learning: Hardware-aware ML
• Search and Optimization: Learning to Search
• Constraint Satisfaction and Optimization: Distributed CSP/Optimization

Application Category

• Security and Privacy: Large-scale security measurements
• Responsible Web: Machine-in-the-loop, human agency and autonomy
• Economics, Online Markets and Human Computation: Incentives in network design for Web infrastructures and ecosystems

Abstract

As the CMOS technology enters nanometer scales, integrated circuits (ICs) become increasingly sensitive to radiation-induced soft errors, which can corrupt the state of storage elements and cause severe reliability issues. Many hardened designs have been proposed to mitigate soft errors by using filtering elements. However, existing filtering elements only protect their inputs against soft errors and leave their outputs unprotected. Therefore, additional filtering elements must be added to protect outputs, resulting in extra overhead. In this paper, we first propose a novel Output-Split C-element (OSC) to protect both its input and output nodes, and then a novel LOw-COst single-node-upset (SNU) self-resilient latch (LOCO) to use OSCs to achieve both soft error resilience and low overhead. The usage of OSCs effectively reduce the short-circuit current of the LOCO latch during switching activities. Furthermore, the usage of clock gating and high-speed path reduces power consumption and delay, respectively. Compared with state-of-the-art SNU-resilient hardened designs, the LOCO latch achieves 19% fewer transistors, 63.58% lower power, 74% less delay, and 92% lower power-delay-product (PDP) on average. In addition, the LOCO latch exhibits better stability under variations in PVT (Process, Voltage, and Temperature).

Problem

• Proposes a novel Output-Split C-element to protect both input and output nodes from soft errors
• Introduces a low-cost latch design to achieve single-node-upset resilience with reduced overhead
• Addresses reliability issues in nanometer CMOS technology by minimizing power, delay, and transistor count

Innovation

• Output-Split C-element protects both input and output nodes
• LOCO latch uses OSCs for soft error resilience with low overhead
• Clock gating and high-speed path reduce power and delay