🤖 AI Summary
DRAM read disturbance phenomena (e.g., RowHammer, RowPress) exhibit persistent discrepancies between empirical measurements and device-level simulations—hindering accurate reliability modeling and hardware-level mitigation design. This work presents the first systematic comparison of measured disturbance behavior across 96 commercial DDR4 chips against state-of-the-art device simulations. We identify fundamental contradictions: (i) bit-flip polarity is inverted relative to predictions from mainstream models, and (ii) disturbance susceptibility exhibits strong, previously unmodeled dependence on access patterns. Through error-mechanism-aware access pattern design, cross-layer validation, and controlled experimental characterization, we expose critical limitations in current DRAM reverse-engineering methodologies and device models—specifically, their lack of physical completeness. These findings challenge foundational assumptions in existing reliability modeling frameworks. Our results provide essential empirical evidence for developing more accurate DRAM disturbance models and robust, hardware-implementation-aware countermeasures.
📝 Abstract
Modern DRAM is vulnerable to read disturbance (e.g., RowHammer and RowPress) that significantly undermines the robust operation of the system. Repeatedly opening and closing a DRAM row (RowHammer) or keeping a DRAM row open for a long period of time (RowPress) induces bitflips in nearby unaccessed DRAM rows. Prior works on DRAM read disturbance either 1) perform experimental characterization using commercial-off-the-shelf (COTS) DRAM chips to demonstrate the high-level characteristics of the read disturbance bitflips, or 2) perform device-level simulations to understand the low-level error mechanisms of the read disturbance bitflips. In this paper, we attempt to align and cross-validate the real-chip experimental characterization results and state-of-the-art device-level studies of DRAM read disturbance. To do so, we first identify and extract the key bitflip characteristics of RowHammer and RowPress from the device-level error mechanisms studied in prior works. Then, we perform experimental characterization on 96 COTS DDR4 DRAM chips that directly match the data and access patterns studied in the device-level works. Through our experiments, we identify fundamental inconsistencies in the RowHammer and RowPress bitflip directions and access pattern dependence between experimental characterization results and the device-level error mechanisms. Based on our results, we hypothesize that either 1) the retention failure based DRAM architecture reverse-engineering methodologies do not fully work on modern DDR4 DRAM chips, or 2) existing device-level works do not fully uncover all the major read disturbance error mechanisms. We hope our findings inspire and enable future works to build a more fundamental and comprehensive understanding of DRAM read disturbance.