WebRISC-V: A 64-bit RISC-V Pipeline Simulator for Computer Architecture Classes

2025-03-30

AI Summary

To address the pedagogical challenge of students struggling to grasp pipelining concepts in computer architecture education, this paper designs and implements a lightweight, pure-front-end web-based simulator for a 64-bit RISC-V six-stage pipeline. Built on HTML5/Canvas and a modular finite-state machine architecture, the simulator supports the RV64IM instruction set without requiring backend services or local installation. It enables cycle-accurate execution, real-time stall annotation, multi-level hardware state inspection, and visualization of data and control hazards. Its key contribution is the first high-fidelity, browser-native RISC-V pipeline simulation framework that dynamically demonstrates forwarding and pipeline stalling mechanisms. Empirical teaching evaluations demonstrate significant improvements in students’ conceptual understanding of hazards, forwarding, and stalls. The simulator has been deployed at scale across multiple universities’ computer architecture courses, validating its pedagogical effectiveness and practical usability.

Technology Category

• Cognitive Modeling & Cognitive Systems: Simulating Human Behavior
• Computer Vision: Low Level & Physics-based Vision
• Search and Optimization: Sampling/Simulation-based Search

Application Category

• Web Mining and Content Analysis: Web data generation and simulation
• Responsible Web: Machine-in-the-loop, human agency and autonomy
• Systems and Infrastructure for Web, Mobile and WoT: Web performance, measurement, and characterization

Abstract

WebRISC-V is a web-based educational tool designed to simulate the pipelined execution of assembly programs according to the RV64IM specifications (64-bit RISC-V processor). The tool allows users to investigate pipeline stalls, understand the internal state of pipeline architectural blocks, and visualize the cycle-by-cycle execution of instructions. WebRISC-V executes directly in a web browser, providing a detailed pipeline execution for RISC-V processors. This paper describes the features of WebRISC-V, compares it with similar tools, and provides an example of its usage in investigating the pipeline.

Problem

• Simulate 64-bit RISC-V pipeline execution for education
• Visualize pipeline stalls and internal processor states
• Provide browser-based RISC-V instruction cycle analysis

Innovation

• Web-based 64-bit RISC-V pipeline simulator
• Visualizes cycle-by-cycle instruction execution
• Supports RV64IM specifications in browser