🤖 AI Summary
Designing signal processing algorithms for ultra-low-power hardware demands maximizing energy efficiency under stringent constraints on parallelism and on-chip memory. To address this, we propose four key techniques: (1) accuracy-guaranteed quasi-spline piecewise polynomial approximation, balancing numerical precision with integer-arithmetic compatibility; (2) conflict-free streaming FFT scheduling and self-sorting FFT variants tailored for multi-bank single-port memory; (3) memory-aware parallelization of Schur decomposition and Toeplitz system solving; and (4) a CMOS power-model-driven, mixed-radix FFT co-optimization framework. Theoretically, we establish constructive theorems and derive tight bounds on parallel and memory complexity. Practically, we deliver implementable scheduling strategies and energy-efficiency–area trade-off curves. These contributions jointly enable high-energy-efficiency domain-specific accelerator design for resource-constrained embedded systems.
📝 Abstract
This thesis develops signal-processing algorithms and implementation schemes under constraints of minimal parallelism and memory space, with the goal of improving energy efficiency of low-power computing hardware. We propose (i) a power/energy consumption model for clocked CMOS logic that supports selecting optimal parallelism, (ii) integer-friendly approximation methods for elementary functions that reduce lookup-table size via constrained piecewise-polynomial (quasi-spline) constructions with accuracy guarantees, (iii) provably conflict-free data placement and execution order for mixed-radix streaming FFT on multi-bank and single-port memories, including a self-sorting FFT variant, and (iv) a parallelism/memory analysis of the fast Schur algorithm for superfast Toeplitz system solving, motivated by echo-cancellation workloads. The results provide constructive theorems, schedules, and design trade-offs enabling efficient specialized accelerators.