🤖 AI Summary
This work proposes an end-to-end automated system to address the challenges of inaccurate component recognition and connectivity inference in the conversion of circuit schematic images into machine-readable netlists. The approach synergistically integrates deep learning, connected-component labeling (CCL), optical character recognition (OCR), and a vision-language model (VLM). Notably, it pioneers the use of VLM for component label assignment, enabling more reliable semantic understanding of schematic elements. Through the coordinated application of these complementary techniques, the system achieves high-fidelity netlist generation. Experimental results demonstrate an overall accuracy of 96.47%, representing a 2.72-fold improvement over the current state-of-the-art method.
📝 Abstract
Current methods for converting circuit schematic images into machine-readable netlists struggle with component recognition and connectivity inference. In this paper, we present SINA, an open-source, fully automated circuit schematic image-to-netlist generator. SINA integrates deep learning for accurate component detection, Connected-Component Labeling (CCL) for precise connectivity extraction, and Optical Character Recognition (OCR) for component reference designator retrieval, while employing a Vision-Language Model (VLM) for reliable reference designator assignments. In our experiments, SINA achieves 96.47% overall netlist-generation accuracy, which is 2.72x higher than state-of-the-art approaches.