Scalable Packet Tracking on FPGAs for Erasure-Coded RDMA over Lossy WANs

2026-09-18

AI Summary

为解决跨数据中心AI工作负载中RDMA在WAN上的丢包问题，提出基于FPGA的COMET设计，实现高效硬件卸载的数据包到达追踪。

Abstract

Modern AI workloads increasingly rely on scale across architectures that interconnect multiple datacenters to form a single "AI factory", overcoming the power and cooling constraints of individual sites. However, extending Remote Direct Memory Access (RDMA) across wide area networks (WANs) introduces fundamental challenges: multi-path packet reordering, high latency, and packet loss that severely degrade performance. While erasure coding (EC) has emerged as a promising mechanism for loss recovery, its effectiveness critically depends on efficient packet arrival tracking implemented in hardware. We present COmpact Multi-path Erasure-coded Tracking (COMET), the first fully hardware-offloaded packet-arrival tracking design implemented on an FPGA-based network interface card (NIC) for multi-path RDMA over lossy WANs. COMET employs a scalable cache-based architecture that supports operation at high link rates. Our evaluation shows that COMET sustains line rate operation at 400 Gbps and beyond. Critically, COMET decouples on-chip memory footprint from link Bandwidth-Delay Product (BDP), and its cache-based architecture (COMET Cache) enables supporting 6 times more concurrent connections than state-of-the-art (SOTA) SoC-based designs. These results demonstrate that scalable, fully hardware-offloaded packet-arrival tracking is practical on FPGA-based NICs at current data rates, and its architectural scalability extends to emerging 1.6 Tbps NICs and beyond.

Problem

• Remote Direct Memory Access (RDMA)
• Wide Area Networks (WANs)
• Erasure Coding (EC)
• Packet Loss
• Scalability

Innovation

• FPGA
• Erasure Coding
• Packet Tracking
• Scalable Architecture
• High-Speed Networks