Technology Category
Search and Optimization: Algorithm ConfigurationConstraint Satisfaction and Optimization: Distributed CSP/OptimizationMachine Learning: Optimization
Bounded Dynamic Level Maintenance for Efficient Logic Optimization
🤖 AI Summary
Traditional algorithms for dynamically updating node levels in circuit DAGs during logic optimization suffer from a worst-case time complexity of O(|V|²) under local changes, severely limiting scalability for large-scale circuits.
Method: This paper proposes the first bounded dynamic level maintenance algorithm, leveraging partial topological order analysis, incremental graph change modeling, and level constraint propagation.
Contribution/Results: The approach reduces theoretical complexity to O(|V|Δ log Δ), overcoming the prior unbounded bottleneck. Evaluated on standard benchmark circuits, it achieves a 1074.8× speedup in level maintenance and a 6.4× end-to-end logic optimization acceleration, while preserving PPA (Power, Performance, Area) quality without degradation.
Technology Category
Application Category
📝 Abstract
Logic optimization constitutes a critical phase within the Electronic Design Automation (EDA) flow, essential for achieving desired circuit power, performance, and area (PPA) targets. These logic circuits are typically represented as Directed Acyclic Graphs (DAGs), where the structural depth, quantified by node level, critically correlates with timing performance. Modern optimization strategies frequently employ iterative, local transformation heuristics (emph{e.g.,} emph{rewrite}, emph{refactor}) directly on this DAG structure. As optimization continuously modifies the graph locally, node levels require frequent dynamic updates to guide subsequent decisions. However, a significant gap exists: existing algorithms for incrementally updating node levels are unbounded to small changes. This leads to a total of worst complexity in $O(|V|^2)$ for given local subgraphs ${ΔG_i}_{i=1}^{|V|}$ updates on DAG $G(V,E)$. This unbounded nature poses a severe efficiency bottleneck, hindering the scalability of optimization flows, particularly when applied to large circuit designs prevalent today. In this paper, we analyze the dynamic level maintenance problem endemic to iterative logic optimization, framing it through the lens of partial topological order. Building upon the analysis, we present the first bounded algorithm for maintaining level constraints, with $O(|V| Δlog Δ)$ time for a sequence $|V|$ of updates ${ΔG_i}$, where $Δ= max_i |ΔG_i|$ denotes the maximum extended size of $ΔG_i$. Experiments on comprehensive benchmarks show our algorithm enables an average 6.4$ imes$ overall speedup relative to
w and
f, driven by a 1074.8$ imes$ speedup in the level maintenance, all without any quality sacrifice.
Problem
Research questions and friction points this paper is trying to address.
Bounded algorithm for dynamic level maintenance in logic optimization
Addresses unbounded complexity in node level updates for DAGs
Improves scalability and efficiency of iterative circuit optimization flows
Innovation
Methods, ideas, or system contributions that make the work stand out.
Bounded algorithm for dynamic level maintenance
Partial topological order for iterative logic optimization
Efficient updates with O(|V|ΔlogΔ) time complexity
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