Technology Category
Machine Learning: Hardware-aware MLComputer Vision: Adversarial Attacks & RobustnessConstraint Satisfaction and Optimization: Satisfiability Modulo Theories
Weight Transformations in Bit-Sliced Crossbar Arrays for Fault Tolerant Computing-in-Memory: Design Techniques and Evaluation Framework
🤖 AI Summary
Stuck-at faults (SAFs) in memristor-based compute-in-memory (CiM) accelerators severely degrade multi-bit DNN inference accuracy. To address this, we propose a retraining-free, zero-overhead weight transformation fault-tolerance method. We introduce two training-agnostic mapping mechanisms: column-level sign-flip and bit-slice-level bit-flip, and design a scalable lookup table (LUT)-based evaluation framework enabling joint fault-aware weight mapping and crossbar voltage margin (CVM) optimization. Evaluated on ResNet-18/50, ViT, CIFAR-100, and ImageNet, our method substantially recovers accuracy under high SAF rates. Hardware analysis shows sign-flip incurs near-zero area and latency overhead, while bit-flip achieves superior fault tolerance with minimal area and delay cost. This work establishes an efficient, scalable reliability enhancement paradigm for CiM systems.
Technology Category
Application Category
📝 Abstract
The deployment of deep neural networks (DNNs) on compute-in-memory (CiM) accelerators offers significant energy savings and speed-up by reducing data movement during inference. However, the reliability of CiM-based systems is challenged by stuck-at faults (SAFs) in memory cells, which corrupt stored weights and lead to accuracy degradation. While closest value mapping (CVM) has been shown to partially mitigate these effects for multibit DNNs deployed on bit-sliced crossbars, its fault tolerance is often insufficient under high SAF rates or for complex tasks. In this work, we propose two training-free weight transformation techniques, sign-flip and bit-flip, that enhance SAF tolerance in multi-bit DNNs deployed on bit-sliced crossbar arrays. Sign-flip operates at the weight-column level by selecting between a weight and its negation, whereas bit-flip provides finer granularity by selectively inverting individual bit slices. Both methods expand the search space for fault-aware mappings, operate synergistically with CVM, and require no retraining or additional memory. To enable scalability, we introduce a look-up-table (LUT)-based framework that accelerates the computation of optimal transformations and supports rapid evaluation across models and fault rates. Extensive experiments on ResNet-18, ResNet-50, and ViT models with CIFAR-100 and ImageNet demonstrate that the proposed techniques recover most of the accuracy lost under SAF injection. Hardware analysis shows that these methods incur negligible overhead, with sign-flip leading to negligible energy, latency, and area cost, and bit-flip providing higher fault resilience with modest overheads. These results establish sign-flip and bit-flip as practical and scalable SAF-mitigation strategies for CiM-based DNN accelerators.
Problem
Research questions and friction points this paper is trying to address.
Enhancing fault tolerance in compute-in-memory DNN accelerators against stuck-at faults
Proposing training-free weight transformations to mitigate accuracy loss from faults
Introducing a scalable framework for optimizing fault-aware weight mappings
Innovation
Methods, ideas, or system contributions that make the work stand out.
Sign-flip technique inverts weight columns for fault tolerance
Bit-flip technique selectively inverts individual bit slices
Look-up-table framework accelerates optimal transformation computation
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