RealProbe: An Automated and Lightweight Performance Profiler for In-FPGA Execution of High-Level Synthesis Designs

2025-04-04

AI Summary

In HLS design, significant discrepancies between tool-reported and FPGA-measured clock cycles lead to erroneous bottleneck identification and suboptimal design decisions; existing on-chip analysis methods rely on manual RTL inspection and signal monitoring, resulting in low efficiency. This paper proposes the first fully automated, in-FPGA performance profiling framework tailored for HLS. It leverages pragma-driven RTL generation, incremental synthesis, and cycle-accurate counter insertion to enable non-intrusive, timing-isolated cycle measurement at both single-instruction and full-function granularity, while supporting automated design-space exploration. Evaluated on 28 large-scale designs, the framework achieves 100% cycle capture accuracy with only 16.98% LUT and 43.15% FF overhead, and zero BRAM utilization.

Technology Category

Machine Learning: Hardware-aware MLPlanning, Routing, and Scheduling: Optimization of Spatio-temporal SystemsCognitive Modeling & Cognitive Systems: Conceptual Inference and Reasoning

Application Category

Systems and Infrastructure for Web, Mobile and WoT: Web performance, measurement, and characterizationSecurity and Privacy: Tracking, profiling, and countermeasures against themWeb Mining and Content Analysis: Web measurements

Abstract

High-level synthesis (HLS) accelerates FPGA design by rapidly generating diverse implementations using optimization directives. However, even with cycle-accurate C/RTL co-simulation, the reported clock cycles often differ significantly from actual FPGA performance. This discrepancy hampers accurate bottleneck identification, leading to suboptimal design choices. Existing in-FPGA profiling tools, such as the Integrated Logic Analyzer (ILA), require tedious inspection of HLS-generated RTL and manual signal monitoring, reducing productivity. To address these challenges, we introduce RealProbe, the first fully automated, lightweight in-FPGA profiling tool for HLS designs. With a single directive--#pragma HLS RealProbe--the tool automatically generates all necessary code to profile cycle counts across the full function hierarchy, including submodules and loops. RealProbe extracts, records, and visualizes cycle counts with high precision, providing actionable insights into on-board performance. RealProbe is non-intrusive, implemented as independent logic to ensure minimal impact on kernel functionality or timing. It also supports automated design space exploration (DSE), optimizing resource allocation based on FPGA constraints and module complexity. By leveraging incremental synthesis and implementation, DSE runs independently of the original HLS kernel. Evaluated across 28 diverse test cases, including a large-scale design, RealProbe achieves 100% accuracy in capturing cycle counts with minimal logic overhead-just 16.98% LUTs, 43.15% FFs, and 0% BRAM usage. The tool, with full documentation and examples, is available on GitHub.

Problem

• Discrepancy between simulated and actual FPGA performance cycles
• Tedious manual inspection in existing in-FPGA profiling tools
• Lack of automated cycle count profiling for HLS designs

Innovation

• Automated in-FPGA profiling with #pragma HLS RealProbe
• Non-intrusive cycle count extraction and visualization
• Automated design space exploration for FPGA optimization